CS4954-CQZR Cirrus Logic Inc, CS4954-CQZR Datasheet - Page 16

• Manufacturer Part Number: CS4954-CQZR
• Description: IC NTSC/PAL Digital Video Encoder
• Manufacturer: Cirrus Logic Inc
• Type: Video Encoderr

Specifications of CS4954-CQZR

• Voltage - Supply, Analog: 3.15 V ~ 5.25 V
• Voltage - Supply, Digital: 3.15 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CDB4955A - EVALUATION BOARD FOR CS4955A
• Applications: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.2
5.2.1 Slave Mode Input Interface
In Slave ITU R.BT601 (not ITU-R.BT656 input)
Mode, the CS4954/5 receives signals on VSYNC
and HSYNC as inputs. Slave Mode is the default
following RESET and is changed to Master Mode
via a control register bit (CONTROL_0 [4]). The
CS4954/5 is limited to ITU R.BT601 horizontal
and vertical input timing. All clocking in the
CS4954/5 is generated from the CLK pin. In Slave
Mode, the Sync Generator uses externally provided
horizontal and vertical sync signals to synchronize
the internal timing of the CS4954/5. Video data that
is sent to the CS4954/5 must be synchronized to the
horizontal and vertical sync signals. Figure
trates horizontal timing for ITU R.BT601 input in
Slave Mode. Note that the CS4954/5 expects to re-
ceive the first active pixel data on clock cycle 245
16
NTSC 27MHz Clock Count
NTSC 27MHz Clock Count
PAL 27MHz Clock Count
PAL 27MHz Clock Count
Video Timing
HSYNC (output)
(SYNC_DLY=0)
(SYNC_DLY=1)
HSYNC (input)
CB (output)
V[7:0]
V[7:0]
V[7:0]
CLK
CLK
active pixel
• • •
• • •
Cb
1682
1702
Y
1682
1702
Y
#719
active pixel
active pixel
Figure 5. ITU R.BT601 Input Master Mode Horizontal Timing
Cr
1683
1703
Cr
Y
1683
1703
Figure 4. ITU R.BT601 Input Slave Mode Horizontal Timing
#720
#720
active pixel
Cr
1684
1704
Y
1684
1704
Y
#720
1685
1705
Y
1685
1705
1686
1706
1686
1706
• • •
• • •
• • •
• • •
4
1716
1728
illus-
1716
1728
horizontal blanking
1
1
horizontal blanking
1
1
horizontal blanking
(NTSC) when CONTROL_2 Register (0x02) bit
SYNC_DLY = 0. When SYNC_DLY = 1, it expects
the first active pixel data on clock cycle 246 (NTSC).
5.2.2 Master Mode Input Interface
The CS4954/5 defaults to Slave Mode following
RESET high but can be switched into Master Mode
via the MSTR bit in the CONTROL_0 Register
(0x00). In Master Mode, the CS4954/5 uses the
VSYNC, HSYNC and FIELD device pins as out-
puts to schedule the proper external delivery of dig-
ital video into the V [7:0] pins. Figure
horizontal timing for the CCIR601 input in Master
Mode.
The timing of the HSYNC output is selectable in
the PROG_HS Registers (0x0D, 0x0E). HSYNC
can be delayed by one full line cycle. The timing of
the VSYNC output is also selectable in the
2
2
2
2
3
3
3
3
• • •
• • •
• • •
• • •
128
128
128
128
129
129
129
129
• • •
• • •
• • •
• • •
244
264
244
264
CS4954 CS4955
active pixel
Cb
active pixel
Cb
245
265
245
265
#1
#1
active pixel
Cb
Y
246
266
Y
246
266
#1
active pixel
active pixel
Cr
Y
Cr
247
267
247
267
#2
#2
5
active pixel
Cr
Y
248
268
illustrates
Y
248
268
DS278F6
#2