CY23FS08OXI-05 Cypress Semiconductor Corp, CY23FS08OXI-05 Datasheet
CY23FS08OXI-05
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CY23FS08OXI-05 Summary of contents
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... PLL Block FBK Decoder 4 S[4:1] Cypress Semiconductor Corporation Document #: 38-07518 Rev. *C Failsafe™ 2.5V/ 3.3V Zero Delay Buffer Functional Description The CY23FS08 is a FailSafe™ Zero Delay Buffer with two reference clock inputs and eight phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure ...
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Pin Definitions Pin Number Pin Name 1,2 REF1,REF2 5V-tolerant, reference clock inputs 4,5,10,11 CLKB[1:4] Bank B clock outputs. 25,24,19,18 CLKA[1:4] Bank A clock outputs. 27 FBK Feedback input to the PLL. 23,6,7,22 S[1:4] Frequency select pins/PLL and DCXO bypass. 14 ...
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FailSafe Function The CY23FS08 is targeted at clock distribution applications that could or which currently require continued operation should the main reference clock fail. Existing approaches to this requirement have utilized multiple reference clocks with either internal or external methods ...
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Reference Reference Off Output Fail#/Safe t FSL Figure 3. FailSafe Timing Diagram: Input Reference Slowly Drifting Out of FailSafe Capture Range Failsafe typical frequency settling time Initial valid Ref1 = 20 MHz +100 ppm, 150 100 Figure ...
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Figure 5. FailSafe Effective Loop Bandwidth (min Figure 6. Sample Timing of Muxing Between Two Reference ...
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Figure 7. Resulting Output Dphase/Cycle Typical Rate of Change (105 MHz ...
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XTAL Selection Criteria and Application Example Choosing the appropriate XTAL will ensure the FailSafe device will be able to span an appropriate frequency of operation. Also, the XTAL parameters will determine the holdover frequency stability. Critical parameters are as follows. ...
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Table 3. Pullability Range from XTAL with Different C0/C1 Ratio C0/C1 Ratio Cload(min.) Cload(max.) 200 8.0 32.0 300 8.0 32.0 400 8.0 32.0 Calculated value of the pullability range for the XTAL with C0/C1 ratio of 200, 300 and 400 ...
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Absolute Maximum Conditions Parameter Description V Supply Voltage DD V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J ESD ESD Protection (Human Body Model) HBM Ø Dissipation, Junction to Case JC Ø ...
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... LOCK Ordering Information Part Number CY23FS08OI CY23FS08OIT CY23FS08OC CY23FS08OCT Lead-free CY23FS08OXI CY23FS08OXIT CY23FS08OXC CY23FS08OXCT Notes The ( φ reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long Parameters guaranteed by design and characterization, not 100% tested in production. ...
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... Document #: 38-07518 Rev. *C © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
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Document History Page Document Title: CY23FS08 Failsafe™ 2.5V/ 3.3V Zero Delay Buffer Document #: 38-07518 Rev. *C Issue REV. ECN NO. Date ** 123699 04/23/03 *A 224067 See ECN RGL/ZJX Changed the XTAL Specifications table. *B 276749 See ECN *C ...