CY62167DV30LL-55BVXIT Cypress Semiconductor Corp, CY62167DV30LL-55BVXIT Datasheet - Page 6

• Manufacturer Part Number: CY62167DV30LL-55BVXIT
• Description: CY62167DV30LL-55BVXIT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62167DV30LL-55BVXIT

• Format - Memory: RAM
• Memory Type: SRAM
• Memory Size: 16M (1M x 16)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VFBGA
• Density: 16Mb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3V
• Address Bus: 20b
• Package Type: BGA
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 30mA
• Operating Supply Voltage (min): 2.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Word Size: 16b
• Number Of Words: 1M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Retention Waveform
Switching Characteristics
Document Number : 38-05328 Rev. *I
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Notes
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
14. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
15. Test conditions for all parameters other than Tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V
16. At any given temperature and voltage condition, t
17. t
18. The internal Write time of the memory is defined by the overlap of WE, CE
Parameter
CE
BHE
to V
device.
and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the Write.
HZOE
1
CC(typ.)
V
CE
,
, t
or
BLE
CC
or
HZCE
2
, and output loading of the specified I
[18]
, t
[15]
HZBE
, and t
Read cycle time
Address to data valid
Data hold from address change
CE
OE LOW to data valid
OE LOW to LOW Z
OE HIGH to High Z
CE
CE
CE
CE
BLE/BHE LOW to data valid
BLE/BHE LOW to Low Z
BLE/BHE HIGH to HIGH Z
Write cycle time
CE
Address set-up to write end
Address hold from write end
Address set-up to write start
WE pulse width
BLE/BHE LOW to write end
Data set-up to write end
Data hold from write end
WE LOW to High-Z
WE HIGH to Low-Z
HZWE
1
1
1
1
1
1
LOW and CE
LOW and CE
HIGH and CE
LOW and CE
HIGH and CE
LOW and CE
transitions are measured when the outputs enter a high impedance state.
[14]
Over the Operating Range
2
2
2
2
2
2
[16]
[16, 17]
[16, 17]
[16]
HIGH to data valid
HIGH to Low Z
HIGH to Power-up
HIGH to write end
LOW to High Z
LOW to Power-down
V
OL
t
HZCE
CC
CDR
/I
Description
OH
, min.
[16]
is less than t
as shown in the “AC Test Loads and Waveforms” section.
[16, 17]
[16]
[16, 17]
LZCE
DATA RETENTION MODE
, t
HZBE
1
= V
IL
is less than t
, BHE and/or BLE = V
V
DR
> 1.5 V
LZBE
, t
HZOE
Min
IL
55
10
10
10
55
40
40
40
40
25
10
–
–
–
5
–
–
0
–
–
0
0
0
–
, and CE
–
is less than t
55 ns
2
Max
55
55
25
20
20
55
55
20
20
= V
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LZOE
IH
CY62167DV30 MoBL
V
. All signals must be ACTIVE to initiate a write
CC
, and t
t
R
, min.
Min
70
10
10
10
70
60
60
45
60
30
10
–
–
–
5
–
–
0
–
–
–
0
0
0
–
HZWE
70 ns
CC(typ)
is less than t
Max
70
70
35
25
25
70
70
25
25
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
/2, input pulse levels of 0
LZWE
Page 6 of 17
for any given
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
