CY7C1315BV18-250BZC Cypress Semiconductor Corp, CY7C1315BV18-250BZC Datasheet - Page 19

• Manufacturer Part Number: CY7C1315BV18-250BZC
• Description: SRAM (Static RAM)
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1315BV18-250BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 18M (512K x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document Number: 38-05620 Rev. *C
Power-Up Sequence in QDR-II SRAM
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power-Up Sequence
Power-up Waveforms
Notes:
17. It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1 Kohm.
18. During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
• Apply power and drive DOFF LOW (All other inputs can be
• After the power and clock (K, K, C, C) are stable take DOFF
• The additional 1024 cycles of clocks are required for the
V
HIGH or LOW)
— Apply V
— Apply V
HIGH
DLL to lock
DD
/
DOFF
V
DDQ
K
K
DD
DDQ
before V
before V
DDQ
REF
Unstable Clock
Clock Start (Clock Starts after
or at the same time as V
V
DD
[17, 18]
/
V
DDQ
REF
V
Stable (< +/- 0.1V DC per 50ns )
DD
/
V
DLL Constraints
DDQ
• DLL uses either K or C clock as its synchronizing input.The
• The DLL will function at frequencies down to 80 MHz
• If the input clock is unstable and the DLL is enabled, then
Fix High (or tied to V DDQ )
input should have low phase jitter, which is specified as
t
the DLL may lock to an incorrect frequency, causing
unstable SRAM behavior
KC Var
> 1024 Stable clock
Stable)
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Start Normal
Operation
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