CY7C1338G-100AXCT Cypress Semiconductor Corp, CY7C1338G-100AXCT Datasheet - Page 7
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CY7C1338G-100AXCT
Manufacturer Part Number
CY7C1338G-100AXCT
Description
CY7C1338G-100AXCT
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1338G-100AXC.pdf
(21 pages)
Specifications of CY7C1338G-100AXCT
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
4M (128K x 32)
Speed
100MHz
Interface
Parallel
Voltage - Supply
3.15 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1338G-100AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Truth Table
Document Number: 38-05521 Rev. *F
Deselected cycle, power-down
Deselected cycle, power-down
Deselected cycle, power-down
Deselected cycle, power-down
Deselected cycle, power-down
Sleep mode, power-down
Read cycle, begin burst
Read cycle, begin burst
Write cycle, begin burst
Read cycle, begin burst
Read cycle, begin burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Write cycle, continue burst
Write cycle, continue burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Write cycle, suspend burst
Write cycle, suspend burst
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more byte write enable signals (BW
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
(BW
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
A
, BW
Cycle Description
B
, BW
[2, 3, 4, 5, 6]
C
, BW
D
), BWE, GW = H.
Address
External
External
External
External
External
Current
Current
Current
Current
Current
Current
Used
None
None
None
None
None
None
Next
Next
Next
Next
Next
Next
CE
A
H
H
H
H
H
H
H
L
L
L
X
X
L
L
L
L
L
X
X
X
X
X
X
, BW
1
CE
B
X
H
H
H
H
H
X
X
X
X
X
X
X
L
X
L
X
X
X
X
X
X
X
, BW
2
C
CE
, BW
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
3
D
ZZ ADSP ADSC ADV WRITE OE CLK
) and BWE = L or GW= L. WRITE = H when all byte write enable signals
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
X
. Writes may occur only on subsequent clocks
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
X
X
X
X
X
X
H
X
H
H
H
X
X
H
H
X
X
L
L
L
L
L
L
CY7C1338G
L-H Tri-state
L-H Tri-state
L-H Tri-state
L-H Tri-state
L-H Tri-state
L-H
L-H Tri-state
L-H
L-H
L-H Tri-state
L-H
L-H Tri-state
L-H
L-H Tri-state
L-H
L-H
L-H
L-H Tri-state
L-H
L-H Tri-state
L-H
L-H
X
Tri-state
Page 7 of 21
DQ
Q
D
Q
Q
Q
D
D
Q
Q
D
D
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