CY7C133-55JC Cypress Semiconductor Corp, CY7C133-55JC Datasheet
CY7C133-55JC
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CY7C133-55JC Summary of contents
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... ADDRESS DECODER A 0L Note: 1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input. Cypress Semiconductor Corporation Document #: 38-06036 Rev Dual-Port Static RAM Functional Description The CY7C133 and CY7C143 are high-speed CMOS dual-port static RAMs. Two ports are provided permitting independent access to any location in memory ...
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... Selection Guide Maximum Access Time Typical Operating Current I CC Typical Standby Current for I SB1 Document #: 38-06036 Rev. *B 68-Pin LCC/PLCC Top View 10L 11 11L 12 12L 13 13L 14 14L 15 15L 16 7C133 17 CC 7C143 2728 29 30 3132 7C133-25 7C143-25 25 170 40 CY7C133 CY7C143 BUSY BUSY 7C133-35 7C133-55 ...
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... To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. The CY7C133 and CY7C143 have an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device ...
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... Read Lower Byte, Write Upper Byte Write to Lower Byte Write to Upper Byte Read to Both Bytes High Impedance Outputs BUSY Function R H Normal H Normal H Normal [4] Note 3 Write Inhibit RIGHT R/W BUSY 5V R/W BUSY Result and BUSY cannot both be LOW simultaneously LOW. R CY7C133 CY7C143 Page ...
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... CC V > V – 0. < 0.2V, Active Port Outputs Open MAX Test Conditions V = Min – < CY7C133 CY7C143 Ambient Temperature ° ° +70 C ° ° − +85 C 7C133-25 7C143-25 Min. Typ. 2.4 2.2 −5 −5 Com’l 170 Ind. 170 [8] Com’l 40 Ind ...
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... Max BUSY OR INT BUSY Output Load (CY7C133 ONLY) ALL INPUT PULSES 90% 90% 10% < Max. Unit −5 µA −200 mA 220 mA 250 110 mA 125 105 Unit 281Ω Page ...
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... HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 15. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of “Read with BUSY, Master: CY7C133.” ...
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... Device is continuously selected 23. Address valid prior to or coincidence with CE transition LOW. Document #: 38-06036 Rev. *B Either Port Address Access Either Port CE/OE Access t ACE t DOE t LZOE Read with BUSY (for master CY7C133 ADDRESS MATCH t PWE ADDRESS MATCH BLA and CY7C133 CY7C143 DATA VALID ...
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... Document #: 38-06036 Rev. *B [24, 25, 26 MATCH MATCH t WDD [17, 27] Either Port SCE PWE t SD DATA VALID HIGH IMPEDANCE for the reading port PWE . SD CY7C133 CY7C143 t DH VALID VALID t DDD allow the data I/O pins to enter high HZWE SD Page ...
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... If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document #: 38-06036 Rev. *B [23, 28] Either Port SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE ADDRESS MATCH BLC ADDRESS MATCH BLC CY7C133 CY7C143 LZWE t BHC t BHC Page ...
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... ADDRESS R BUSY R Right Address Valid First: ADDRESS MATCH ADDRESS ADDRESS L BUSY L Busy Timing Diagram No. 3 Write with BUSY (For Slave CY7C143 BUSY Document #: 38-06036 Rev ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA t PWE CY7C133 CY7C143 t WH Page ...
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... CY7C133-35JC CY7C133-35JI 55 CY7C133-55JC Package Diagram All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-06036 Rev. *B © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...
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... Document History Page Document Title: CY7C133/CY7C143 Dual-Port Static RAM Document Number: 38-06036 Issue REV. ECN NO. Date ** 110178 09/22/01 *A 127954 08/27/03 *B 236761 See ECN Document #: 38-06036 Rev. *B Orig. of Change SZV Change from Spec number: 38-00414 to 38-06036 FSG Logic Block Diagram: fixed busy I/O flag on devices (typo) Removed obsolete parts from ordering information table: – ...