CY7C133-25JC Cypress Semiconductor Corp, CY7C133-25JC Datasheet

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CY7C133-25JC

Manufacturer Part Number
CY7C133-25JC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C133-25JC

Density
32Kb
Access Time (max)
25ns
Operating Supply Voltage (typ)
5V
Package Type
LCC
Operating Temp Range
0C to 70C
Supply Current
250mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
68
Word Size
16b
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C133-25JC
Manufacturer:
CYPRESS
Quantity:
1 831
Cypress Semiconductor Corporation
Document #: 38-06036 Rev. *B
Features
Note:
1.
• True dual-ported memory cells which allow
• 2K x 16 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 25/35/55 ns
• Low operating power: I
• Fully asynchronous operation
• Master CY7C133 expands data bus width to 32 bits or
• BUSY output flag on CY7C133; BUSY input flag on
• Available in 68-pin PLCC
Logic Block Diagram
simultaneous reads of the same memory location
more using slave CY7C143
CY7C143
CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.
R/W
R/W
I/O
I/O
OE
CE
8L
LUB
LLB
0L
BUSY
– I/O
L
L
– I/O
L
A
A
15L
[1]
0L
10L
7L
CC
= 150 mA (typ.)
DECODER
ADDRESS
R/W
R/W
CE
OE
LUB
LLB
CONTROL
L
L
I/O
3901 North First Street
(CY7C133 ONLY)
ARBITRA TION
MEMORY
ARRAY
LOGIC
Functional Description
The CY7C133 and CY7C143 are high-speed CMOS 2K by 16
dual-port static RAMs. Two ports are provided permitting
independent access to any location in memory. The CY7C133
can be utilized as either a stand-alone 16-bit dual-port static
RAM or as a master dual-port RAM in conjunction with the
CY7C143 slave dual-port device in systems requiring 32-bit or
greater word widths. It is the solution to applications requiring
shared or buffered data, such as cache memory for DSP,
bit-slice, or multiprocessor designs.
Each port has independent control pins; Chip Enable (CE),
Write Enable (R/W
BUSY signals that the port is trying to access the same
location currently being accessed by the other port. An
automatic power-down feature is controlled independently on
each port by the Chip Enable (CE) pin.
The CY7C133 and CY7C143 are available in 68-pin PLCC.
2K x 16 Dual-Port Static RAM
CONTROL
I/O
CE
OE
R/W
R/W
DECODER
ADDRESS
R
R
RLB
RUB
San Jose
UB
, R/W
,
CA 95134
LB
), and Output Enable (OE).
I/O
I/O
BUSY
A
A
Revised June 22, 2004
10R
0R
8R
0R
– I/O
– I/O
R
CE
R/W
R/W
OE
[ ]
1
R
R
RUB
RLB
15R
7R
408-943-2600
CY7C133
CY7C143

Related parts for CY7C133-25JC

CY7C133-25JC Summary of contents

Page 1

... ADDRESS DECODER A 0L Note: 1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input. Cypress Semiconductor Corporation Document #: 38-06036 Rev Dual-Port Static RAM Functional Description The CY7C133 and CY7C143 are high-speed CMOS dual-port static RAMs. Two ports are provided permitting independent access to any location in memory ...

Page 2

... Selection Guide Maximum Access Time Typical Operating Current I CC Typical Standby Current for I SB1 Document #: 38-06036 Rev. *B 68-Pin LCC/PLCC Top View 10L 11 11L 12 12L 13 13L 14 14L 15 15L 16 7C133 17 CC 7C143 2728 29 30 3132 7C133-25 7C143-25 25 170 40 CY7C133 CY7C143 BUSY BUSY 7C133-35 7C133-55 ...

Page 3

... To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. The CY7C133 and CY7C143 have an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device ...

Page 4

... Read Lower Byte, Write Upper Byte Write to Lower Byte Write to Upper Byte Read to Both Bytes High Impedance Outputs BUSY Function R H Normal H Normal H Normal [4] Note 3 Write Inhibit RIGHT R/W BUSY 5V R/W BUSY Result and BUSY cannot both be LOW simultaneously LOW. R CY7C133 CY7C143 Page ...

Page 5

... CC V > V – 0. < 0.2V, Active Port Outputs Open MAX Test Conditions V = Min – < CY7C133 CY7C143 Ambient Temperature ° ° +70 C ° ° − +85 C 7C133-25 7C143-25 Min. Typ. 2.4 2.2 −5 −5 Com’l 170 Ind. 170 [8] Com’l 40 Ind ...

Page 6

... Max BUSY OR INT BUSY Output Load (CY7C133 ONLY) ALL INPUT PULSES 90% 90% 10% < Max. Unit −5 µA −200 mA 220 mA 250 110 mA 125 105 Unit 281Ω Page ...

Page 7

... HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 15. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of “Read with BUSY, Master: CY7C133.” ...

Page 8

... Device is continuously selected 23. Address valid prior to or coincidence with CE transition LOW. Document #: 38-06036 Rev. *B Either Port Address Access Either Port CE/OE Access t ACE t DOE t LZOE Read with BUSY (for master CY7C133 ADDRESS MATCH t PWE ADDRESS MATCH BLA and CY7C133 CY7C143 DATA VALID ...

Page 9

... Document #: 38-06036 Rev. *B [24, 25, 26 MATCH MATCH t WDD [17, 27] Either Port SCE PWE t SD DATA VALID HIGH IMPEDANCE for the reading port PWE . SD CY7C133 CY7C143 t DH VALID VALID t DDD allow the data I/O pins to enter high HZWE SD Page ...

Page 10

... If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document #: 38-06036 Rev. *B [23, 28] Either Port SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE ADDRESS MATCH BLC ADDRESS MATCH BLC CY7C133 CY7C143 LZWE t BHC t BHC Page ...

Page 11

... ADDRESS R BUSY R Right Address Valid First: ADDRESS MATCH ADDRESS ADDRESS L BUSY L Busy Timing Diagram No. 3 Write with BUSY (For Slave CY7C143 BUSY Document #: 38-06036 Rev ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA t PWE CY7C133 CY7C143 t WH Page ...

Page 12

... Ordering Information Master Dual-Port SRAM Speed (ns) Ordering Code 25 CY7C133-25JC CY7C133-25JI 35 CY7C133-35JC CY7C133-35JI 55 CY7C133-55JC Package Diagram All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-06036 Rev. *B © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...

Page 13

... Document History Page Document Title: CY7C133/CY7C143 Dual-Port Static RAM Document Number: 38-06036 Issue REV. ECN NO. Date ** 110178 09/22/01 *A 127954 08/27/03 *B 236761 See ECN Document #: 38-06036 Rev. *B Orig. of Change SZV Change from Spec number: 38-00414 to 38-06036 FSG Logic Block Diagram: fixed busy I/O flag on devices (typo) Removed obsolete parts from ordering information table: – ...

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