CY7C133-25JC Cypress Semiconductor Corp, CY7C133-25JC Datasheet - Page 7

• Manufacturer Part Number: CY7C133-25JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C133-25JC

• Density: 32Kb
• Access Time (max): 25ns
• Operating Supply Voltage (typ): 5V
• Package Type: LCC
• Operating Temp Range: 0C to 70C
• Supply Current: 250mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Word Size: 16b
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06036 Rev. *B
Switching Characteristics
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
Busy/Interrupt Timing (for master CY7C133)
t
t
t
t
t
t
t
t
Busy Timing (for slave CY7C143)
t
t
t
t
Notes:
10. AC Test Conditions use V
11. At any given temperature and voltage condition for any given device, t
12. t
13. This parameter is guaranteed but not tested.
14. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal
15. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of “Read with BUSY, Master: CY7C133.”
16. t
17. To ensure that the earlier of the two ports wins.
18. To ensure that write cycle is inhibited during contention.
19. To ensure that a write cycle is completed after contention.
20. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of “Read with Port-to-port Delay.”
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
BLA
BHA
BLC
BHC
WDD
DDD
BDD
PS
WB
WH
WDD
DDD
9.
Parameter
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
LZCE
OL
BDD
/I
OH,
is a calculated parameter and is greater of 0,t
, t
LZWE
and 30-pF load capacitance.
[14]
, t
HZOE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
R/W Pulse Width
Data Set-up to Write End
Data Hold from Write End
R/W LOW to High Z
R/W HIGH to Low Z
BUSY Low from Address Match
BUSY High from Address Mismatch
BUSY Low from CE LOW
BUSY High from CE HIGH
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
BUSY High to Valid Data
Arbitration Priority Set Up Time
Write to BUSY
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
, t
LZOE
, t
OH
HZCE
= 1.6V and V
and t
[18]
Description
HZWE
Over the Operating Range
[11, 12,13]
[11, 12,13]
[11, 12,13]
[11, 12,13]
[12,13]
[12,13]
OL
[10]
are tested with C
[13]
[10]
[10]
[19]
= 1.4V.
[16]
[13]
[15]
[20]
WDD
[17]
–t
WP
L
[15]
[20]
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
(actual) or t
LZCE
[9]
Min.
DDD
25
25
20
20
20
15
20
is less than t
0
3
3
0
2
0
0
0
5
0
7C133-25
7C143-25
–t
DW
(actual).
Note 16
Max.
25
25
20
15
15
25
15
25
20
20
20
50
35
50
35
HZCE
and t
Min.
LZOE
35
35
25
25
25
20
25
0
3
5
0
2
0
0
0
5
0
7C133-35
7C143-35
is less than t
Note 16
Max.
35
35
25
20
20
25
20
35
30
25
20
60
45
60
45
HZOE
.
Min.
55
55
40
40
35
20
30
0
3
5
0
2
0
0
0
5
0
7C133-55
7C143-55
Note 16
CY7C133
CY7C143
Max.
55
55
30
25
20
25
20
50
40
35
30
80
55
80
55
Page 7 of 13
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns