CY7C1412AV18-200BZI Cypress Semiconductor Corp, CY7C1412AV18-200BZI Datasheet - Page 7

• Manufacturer Part Number: CY7C1412AV18-200BZI
• Description: CY7C1412AV18-200BZI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1412AV18-200BZI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 36M (2M x 18)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Echo Clocks
Echo clocks are provided on the QDR-II to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free-running clocks and are
synchronized to the output clock (C/C) of the QDR-II. In single
clock mode, CQ is generated with respect to K and CQ is
generated with respect to K. The timing for the echo clocks is
shown in the
Application Example
Figure 1
Document #: 38-05615 Rev. *H
MASTER
ASIC)
(CPU
BUS
or
shows two QDR-II used in an application.
CLKIN/CLKIN#
Switching Characteristics
Delayed K#
DATA OUT
Delayed K
Source K#
Source K
Address
DATA IN
BWS#
WPS#
RPS#
Vt
R
R
R = 50ohms
D
A
on page 21.
R
P
S
#
Vt = Vddq/2
W
P
S
#
SRAM #1
Figure 1. Application Example
W
B
S
#
C C#
CQ/CQ#
K
ZQ
K#
Q
R = 250ohms
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL is locked after 1024 cycles of stable clock. The DLL can also
be reset by slowing or stopping the input clock K and K for a
minimum of 30 ns. However, it is not necessary to reset the DLL
to lock to the desired frequency. The DLL automatically locks
1024 clock cycles after a stable clock is presented. The DLL may
be disabled by applying ground to the DOFF pin. For information
refer to the application note
QDRII/DDRII/QDRII+/DDRII+.
D
A
R
Vt
Vt
R
P
S
#
W
P
S
#
AN5062, DLL Considerations in
W
B
S
#
SRAM #2
CY7C1412AV18
CY7C1414AV18
C C#
CQ/CQ#
K
ZQ
K#
Q
R = 250ohms
Page 7 of 27
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