CY7C1460AV25-167AXC Cypress Semiconductor Corp, CY7C1460AV25-167AXC Datasheet

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... Pb-free and non Pb-free 209-ball FBGA package IEEE 1149.1 JTAG-Compatible Boundary Scan ■ Burst capability—linear or interleaved burst order ■ “ZZ” sleep mode option and stop clock option ■ Logic Block Diagram – CY7C1460AV25 (1 M × 36) ADDRESS A0, A1, A REGISTER 0 MODE CLK C ...

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... ARRAY CONTROL LOGIC DRIVERS INPUT REGISTER 1 READ LOGIC Sleep Control ADDRESS REGISTER BURST A0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 WRITE REGISTRY MEMORY AND DATA COHERENCY WRITE ARRAY CONTROL LOGIC DRIVERS INPUT REGISTER 1 READ LOGIC Sleep Control CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 DQs DQP T a ...

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... V TAP AC Test Conditions ....................................... 15 2.5 V TAP AC Output Load Equivalent ......................... 15 1.8 V TAP AC Test Conditions ....................................... 15 1.8 V TAP AC Output Load Equivalent ......................... 15 TAP DC Electrical Characteristics and Operating Conditions ..................................................... 15 Document Number: 38-05354 Rev. *G CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Identification Register Definitions ................................ 15 Scan Register Sizes ....................................................... 16 Identification Codes ....................................................... 16 165-ball FBGA Boundary Scan Order ........................... 17 209-ball FBGA Boundary Scan Order ...

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... DQa 18 63 DQa DQb DDQ 61 DDQ DQa DQb 22 59 DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 54 DDQ DQa DQa DQPa CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 167 MHz Unit 3.4 ns 335 mA 120 DDQ DQP 74 DQa 73 DQa DDQ DQa 69 DQa × 18 DQa 63 DQa DDQ ...

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... DDQ DDQ N DQP DDQ P NC/144M NC/72M MODE NC/576M NC/1G A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M NC/72M MODE A Document Number: 38-05354 Rev. *G CY7C1460AV25 (1 M × 36 CEN CLK TDI A1 TDO TCK TMS CY7C1462AV25 (2 M × 18) ...

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... DDQ MODE A NC/72M TDI Pin Description controls DQ a and DQP , BW controls DQ and DQP and DQP BW controls DQ and DQP CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 DQb DQb 3 BWS DQb BWS DQb b f BWS BWS DQb DQb DQb DQb DQPf DQPb DDQ DDQ DQf V V DQf ...

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... The direction of the pins is X –DQ are placed in a tri-state condition. The outputs are automati controlled DQP is controlled controlled DQP is controlled DQP is controlled CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 . During [31:0] , DQP is controlled DQP is controlled Page [+] Feedback ...

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... CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Single Read /DQP for CY7C1464AV25, a,b,c,d,e,f,g,h for CY7C1460AV25 and DQ /DQP a,b,c,d a,b /DQP for CY7C1464AV25, a,b,c,d,e,f,g,h for CY7C1460AV25 and DQ /DQP a,b,c,d a,b for CY7C1464AV25, BW a,b,c,d for CY7C1462AV25) signals. The a,b Page for a,b ...

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... WE inputs are ignored and the burst counter is incremented. The correct BW (BW for CY7C1464AV25, BW a,b,c,d,e,f,g,h for CY7C1460AV25 and BW for CY7C1462AV25) inputs must a,b be driven in each cycle of the burst write in order to write the correct bytes of data. ...

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... X External Next External Next External Next None Next Current None =data when OE is active. s CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 BW OE CEN CLK L-H Tri-state L-H Tri-state L-H Data out ( L-H Data out ( L-H Tri-state L-H Tri-state L-H Data in ( L-H Data in ( L-H Tri-state L-H ...

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... Partial Write Cycle Description Function (CY7C1460AV25) Read Write – no bytes written Write byte a – (DQ and DQP ) a a Write byte b – (DQ and DQP ) b b Write bytes b, a Write byte c – (DQ and DQP ) c c Write bytes c, a Write bytes c, b Write bytes Write byte d – (DQ ...

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... This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 2.5V/1.8V I/O logic level. The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature ...

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... The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Page ...

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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE UNDEFINED Description / ns CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 TDOV t TDOX Min Max Unit 50 – ns – 20 MHz 20 – – ns – ...

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... DDQ CY7C1462AV25 CY7C1464AV25 (2 M × 18) (512 K × 72) 000 000 000 01011 01011 01011 001000 001000 001000 100111 010111 110111 00000110100 00000110100 CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 – 0.2 DDQ 0.9V 50 50 20pF O Min Max Unit 1.7 – V 2.1 – V 1.6 – V – ...

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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document Number: 38-05354 Rev. *G Bit Size (× 36) Bit Size (× 18 – – Description CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Bit Size (× 72 – 138 Page [+] Feedback ...

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... FBGA Boundary Scan Order CY7C1460AV25 (1 M × 36), CY7C1462AV25 (2 M × 18) Bit# Ball ID Bit N10 28 4 P11 P10 34 10 R10 35 11 R11 36 12 H11 37 13 N11 38 14 M11 39 15 L11 40 16 K11 41 17 J11 42 18 M10 43 19 L10 44 20 K10 45 21 ...

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... C2 A11 91 C1 A10 100 H2 C7 101 H1 B7 102 J2 A7 103 J1 D6 104 K1 G6 105 N6 CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Bit# Ball ID 106 K3 107 K4 108 K6 109 K2 110 L2 111 L1 112 M2 113 M1 114 N2 115 N1 116 P2 117 P1 118 R2 119 R1 120 T2 121 T1 122 U2 123 U1 124 V2 125 V1 126 W2 ...

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... All speed grades DD  V  /2), undershoot: V (AC) > –2 V (Pulse width less than t CYC IL (min) within 200 ms. During this time V < V and CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Ambient DDQ Temperature 2.5 V – 1 –40 °C to +85 °C Min Max Unit 2.375 2.625 2.375 ...

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... EIA/JESD51 317  3 DDQ GND 351  INCLUDING JIG AND SCOPE ( 1667  2 DDQ GND 1538  INCLUDING JIG AND SCOPE (b) CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 165 FBGA 209 FBGA Unit Max Max 165 FBGA 209 FBGA Unit Package Package 20.8 25.31 ° ...

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... V. DDQ is the time power needs to be supplied above V DD and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 –200 –167 Unit Min Max Min Max 1 – 1 – ...

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... READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED [27, 28, 30 D(A1) Q(A2) Q(A3) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE is LOW. When CE is HIGH HIGH CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 OEV CHZ Q(A4) Q(A4+1) D(A5) Q(A6) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) ...

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... Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 32. I/Os are in high Z when exiting ZZ sleep mode. Document Number: 38-05354 Rev ZZREC t RZZI DESELECT or READ Only High-Z DON’T CARE CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Page [+] Feedback ...

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... Speed Package (MHz) Ordering Code Diagram 167 CY7C1460AV25-167AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free CY7C1460AV25-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 × 17 × 1.4 mm) CY7C1462AV25-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 × 17 × 1.4 mm) CY7C1460AV25-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 × ...

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... Package Diagrams Figure 1. 48-pin VFBGA 6 × 8 × 1.0 mm, 51-85150 Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm), 51-85165 Document Number: 38-05354 Rev. *G CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 51-85050 * C 51-85165 *B Page [+] Feedback ...

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... Figure 3. 209-ball FBGA ( 1.76 mm), 51-85167 Document Number: 38-05354 Rev. *G CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 51-85167 *A Page [+] Feedback ...

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... TCK test clock TMS test mode select TDI test data-in TDO test data-out TQFP thin quad flat pack WE write enable Document Number: 38-05354 Rev. *G CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA ...

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... Document History Page Document Title: CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05354 REV. ECN No. Issue Date ** 254911 See ECN *A 303533 See ECN *B 331778 See ECN *C 417547 See ECN *D 473650 See ECN ...

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... Document Title: CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05354 *F 3023843 09/28/2010 *G 3067448 10/21/2010 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office ...