CY7C1480BV25-167AXC Cypress Semiconductor Corp, CY7C1480BV25-167AXC Datasheet - Page 22

• Manufacturer Part Number: CY7C1480BV25-167AXC
• Description: CY7C1480BV25-167AXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1480BV25-167AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range. Timing reference level is 1.25 V when V
Waveforms” on page 21
Notes
Document Number: 001-15143 Rev. *F
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
15. This part has an internal voltage regulator; t
16. t
17. At any possible voltage and temperature, t
18. This parameter is sampled and not 100% tested.
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
ADVH
WEH
DH
CEH
from steady-state voltage.
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High-Z before Low-Z under the same system conditions.
CHZ
Parameter
, t
CLZ
, t
OELZ
, and t
OEHZ
V
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to Low-Z
Clock to High-Z
OE LOW to output valid
OE LOW to output Low-Z
OE HIGH to output High-Z
Address setup before CLK rise
ADSC, ADSP setup before CLK rise
ADV setup before CLK rise
GW, BWE, BW
Data input setup before CLK rise
Chip enable setup before CLK rise
Address hold after CLK rise
ADSP, ADSC hold after CLK rise
ADV hold after CLK rise
GW, BWE, BW
Data input hold after CLK rise
Chip enable hold after CLK rise
DD
unless otherwise noted.
are specified with AC test conditions shown in part (b) of
(typical) to the first access
OEHZ
[16, 17, 18]
X
X
[16, 17, 18]
POWER
setup before CLK rise
hold after CLK rise
Description
is less than t
is the time that the power is supplied above V
[16, 17, 18]
[16, 17, 18]
OELZ
[15]
and t
CHZ
is less than t
DDQ
“AC Test Loads and Waveforms” on page
CLZ
= 2.5 V. Test conditions shown in (a) of
Min
4.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
0
to eliminate bus contention between SRAMs when sharing the same data
250 MHz
CY7C1482BV25, CY7C1486BV25
DD
(minimum) initially before a read or write operation can be initiated.
Max
3.0
3.0
3.0
3.0
Min
5.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
0
200 MHz
Max
3.0
3.0
3.0
3.0
21. Transition is measured ±200 mV
CY7C1480BV25
Min
6.0
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
0
167 MHz
“AC Test Loads and
Max
3.4
3.4
3.4
3.4
Page 22 of 31
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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