CY7C4245-15ASXC Cypress Semiconductor Corp, CY7C4245-15ASXC Datasheet - Page 15

• Manufacturer Part Number: CY7C4245-15ASXC
• Description: CY7C4245-15ASXC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4245-15ASXC

• Function: Synchronous
• Memory Size: 72K (4K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Configuration: Dual
• Density: 72Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 4Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 45mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Notes:
28. PAF offset = m. Number of data words written into FIFO already = 64 − m + 1 for the CY7C4425, 256 − m + 1 for the CY7C4205, 512 − m + 1 for the CY7C4215. 1024
29. PAF is offset = m.
30. 64 − m words in CY7C4425, 256 – m words in CY7C4205, 512 − m words in CY7C4215. 1024 – m words in CY7C4225, 2048 − m words in CY7C4235, and 4096 – m
31. 64 − m + 1 words in CY7C4425, 256 − m + 1 words in CY7C4205, 512 − m + 1 words in CY7C4215, 1024 − m + 1 CY7C4225, 2048 − m + 1 in CY7C4235, and 4096
32. If a write is performed on this rising edge of the write clock, there will be Full – (m–1) words of the FIFO when PAF goes LOW.
33. PAF offset = m.
34. t
− m + 1 for the CY7C4225, 2048 − m + 1 for the CY7C4235, and 4096 − m + 1 for the CY7C4245.
words in CY7C4245.
− m + 1 words in CY7C4245.
and the rising edge of WCLK is less than t
SKEW3
Document Number: 001-45652 Rev. *A
RCLK
WCLK
WCLK
PAF
RCLK
WEN
is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK
WEN
REN
PAF
REN
[29]
Figure 16. Programmable Almost Full Flag Timing (applies only in SMODE (SMODE in LOW))
t
CLKH
(continued)
FULL – M + 1 WORDS
SKEW3
IN FIFO
Figure 15. Programmable Almost Full Flag Timing
t
CLKH
, then PAF may not change state until the next WCLK rising edge.
t
ENS
t
ENH
t
CLKL
Note 28
Note 33
Note 32
t
ENS
t
ENH
t
CLKL
t
PAF
t
PAF
t
t
ENS
ENS
FULL − M WORDS
t
SKEW3
FULL − M WORDS
IN FIFO
IN FIFO
t
ENS
[34]
[30]
t
PAF
t
[30]
ENH
CY7C4425/4205/4215
CY7C4225/4235/4245
FULL − M + 1 WORDS
t
IN FIFO
PAFsynch
[31]
Page 15 of 22
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