CY7C4265-10ASXC Cypress Semiconductor Corp, CY7C4265-10ASXC Datasheet - Page 4

• Manufacturer Part Number: CY7C4265-10ASXC
• Description: IC,FIFO,16KX18,SYNCHRONOUS,CMOS,QFP,64PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4265-10ASXC

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Data Rate: 100MHz
• Access Time: 8ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3. Pin Definitions
Document #: 38-06004 Rev. *G
D
Q
WEN
REN
WCLK
RCLK
WXO/HF
EF
FF
PAE
PAF
LD
FL/RT
WXI
RXI
RXO
RS
OE
V
Signal Name
CC
0 –17
0–17
/SMODE
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
Read Clock
Write Expansion
Out/Half Full Flag
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Load
First Load/
Retransmit
Write Expansion
Input
Read Expansion
Input
Read Expansion
Output
Reset
Output Enable
Synchronous
Almost Empty/
Almost Full Flags
Description
I/O
O Data outputs for an 18-bit bus.
O Dual-Mode Pin:
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
O Cascaded – Connected to RXI of next device.
I
I
I
I
I
I
I
I
I
I
I
I
Data inputs for an 18-bit bus.
Enables the WCLK input.
Enables the RCLK input.
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset
register.
Single device or width expansion – Half Full status flag.
Cascaded – Write Expansion Out signal, connected to WXI of next device.
programmed into the FIFO. PAE is asynchronous when V
is synchronized to RCLK when V
programmed into the FIFO. PAF is asynchronous when V
is synchronized to WCLK when V
When LD is LOW, D
mable-flag-offset register.
Dual-Mode Pin:
Cascaded – The first device in the daisy chain has FL tied to V
has FL tied to V
devices.
Not Cascaded – Tied to V
by strobing RT.
Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to V
Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to V
Resets device to empty condition. A reset is required before an initial read or write
operation after power up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Dual-Mode Pin:
Asynchronous Almost Empty/Almost Full flags – tied to V
Synchronous Almost Empty/Almost Full flags – tied to V
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
CC
. In standard mode or width expansion, FL is tied to V
0–17
(Q
SS
SS
SS
. Retransmit function is also available in stand-alone mode
0–17
.
.
) are written (read) into (from) the program-
CC
CC
/SMODE is tied to V
/SMODE is tied to V
Function
SS
SS
SS
CC
CC
CC
.
.
.
/SMODE is tied to V
/SMODE is tied to V
.
SS
; all other devices
SS
CY7C4265
on all
Page 4 of 25
CC
CC
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