CY7C63613C-SXC Cypress Semiconductor Corp, CY7C63613C-SXC Datasheet
CY7C63613C-SXC
Specifications of CY7C63613C-SXC
CY7C63613C-SXC
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CY7C63613C-SXC Summary of contents
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... CMOS outputs. The CY7C63613C has 12 GPIO pins (Ports that are rated typical sink current. The CY7C63613C has 4 GPIO pins (Port 3) that are rated typical sink current, which allows these pins to drive LEDs. ...
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... The CY7C63413C, CY7C63513C CY7C63613C have 8 Kbytes of EPROM. These parts include Power-on Reset logic, a Watch Dog Timer, a vectored interrupt controller, and a 12-bit free-running timer. The Power-On Reset (POR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000 ...
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... Power-on DAC Reset PORT Note: 1. CY7C63613C is not bonded out for all GPIO pins shown in Logic Block Diagram. Refer to pin configuration diagram for bonded out pins. See note on page 12 for firmware code needed for unused GPIO pins. . Document #: 38-08027 Rev. *B Pin Configuration ...
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... DAC[1:0] offer a programmable range of 3 typical. DAC[7:2] have a program- mable sink current range of 0.2 to 1.0 mA typical. DAC I/O Port not bonded out on CY7C63613C. See note on page 12 for firmware code needed for unused pins. 6-MHz ceramic resonator or external clock input ...
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... Document #: 38-08027 Rev. *B CY7C63413C CY7C63513C CY7C63613C Data The “Data” address mode refers to a data operand that is actually a constant encoded in the instruction example, consider the instruction that loads A with the constant 0xE8: • ...
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... AND [X+expr],A 7 XOR [expr],A 8 XOR [X+expr],A 4 IOWX [X+expr] 5 CPL 6 ASL 4 ASR 5 RLC RRC 4 RET RETI JNC 5 JACC 5 INDEX CY7C63413C CY7C63513C CY7C63613C operand opcode cycles 20 4 acc direct 23 7 index 24 8 acc direct 27 7 index 28 8 address 29 5 address 2A ...
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... USB address A endpoint 2 interrupt vector 0x000E Reserved 0x0010 Reserved 0x0012 Reserved 0x0014 DAC interrupt vector 0x0016 GPIO interrupt vector 0x0018 Reserved 0x001A Program Memory begins here ( bytes) 0x1FDF 8-KB PROM ends here (CY7C63413C, CY7C63513C, CY7C63613C) CY7C63413C CY7C63513C CY7C63613C Page [+] Feedback ...
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... Program Stack begins here and grows upward Data Stack begins here and grows downward The user determines the amount of memory required User Variables USB FIFO for Address A endpoint 2 USB FIFO for Address A endpoint 1 USB FIFO for Address A endpoint 0 CY7C63413C CY7C63513C CY7C63613C Page [+] Feedback ...
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... Processor Status & Control 0xFF Note: 2. DAC I/O Port not bonded out on CY7C63613C. See note on page 12 for firmware code needed for unused GPIO pins. Document #: 38-08027 Rev. *B lator to the selected port. Indexed I/O Write (IOWX) adds the contents the address in the instruction to form the port address and writes data from the accumulator to the specified port ...
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... LOW to HIGH. In addition to the normal reset 2.048 ms WDR goes high Execution begins at for 2.048 ms Reset Vector 0X00 Figure 3. Watch Dog Reset (WDR) CY7C63413C CY7C63513C CY7C63613C XTALOUT XTALIN voltage and the USB IO are the part will start a 96- SS has stabilized, ...
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... Figure 4. Block Diagram of a GPIO Line Port 0 Data P0[4] P0[3] R/W R/W Port 1 Data P1[4] P1[3] R/W R/W Port 2 Data P2[4] P2[3] R/W R/W CY7C63413C CY7C63513C CY7C63613C GPIO Pin ESD P0[2] P0[1] P0[0] R/W R/W R/W P1[2] P1[1] P1[0] R/W R/W R/W P2[2] P2[1] ...
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... Therefore unused port bit is programmed in open-drain mode, it must be written with a ‘0.’ Notice that the CY7C63613C will always require that data bits P1[7:4], P2[7:0], P3[3:0] and DAC[7:0] be written with a ‘0’. ...
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... Config Bit 0 Config Bit 1 Config Bit Table 12.GPIO Configuration Register KΩ 4 bits Isink Isink DAC Register to Interrupt Controller Figure 5. Block Diagram of DAC Port CY7C63413C CY7C63513C CY7C63613C Interrupt Polarity - disabled disabled - + (default Port 1 Port 0 Port 0 Config Bit 1 Config Bit DAC I/O Pin ...
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... DAC Port Interrupt Enable DAC[4] DAC[3] DAC[ DAC Port Interrupt Polarity DAC[4] DAC[3] DAC[ DAC Port Interrupt Polarity Isink[3] Isink[ CY7C63413C CY7C63513C CY7C63613C High current outputs 3 typical DAC[1] DAC[0] R/W R/W DAC[1] DAC[ DAC[1] DAC[ Isink Value Isink[1] Isink[ Page [+] Feedback ...
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... Figure 17. This is a read/write register. All reserved bits must be written to zero. All bits in the register are cleared during reset. USB Status and Control Register 4 3 D– Bus Activity Control Bit 2 R R/W R/W CY7C63413C CY7C63513C CY7C63613C Control Control Bit 1 Bit 0 R/W R/W Page [+] Feedback ...
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... R/W R/W USB Device EPA0, Mode Register Acknowledge Mode Bit 3 R/W R/W USB Device Endpoint Mode Register Acknowledge Mode Bit 3 R/W R/W CY7C63413C CY7C63513C CY7C63613C Device Device Address Address Bit 2 Bit 1 Bit 0 R/W R/W R/W Mode Mode Mode Bit 2 Bit 1 Bit 0 ...
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... Valid bit 6 is used for OUT and set-up tokens only. Data 0/1 Toggle bit 7 selects the DATA packet’s toggle state: 0 for DATA0, 1 for DATA1. USB Device Counter Registers Reserved Byte count Byte count Bit 3 Bit 2 R/W R/W R/W CY7C63413C CY7C63513C CY7C63613C Byte count Byte count Bit 1 Bit 0 R/W R/W Page [+] Feedback ...
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... Suspend, Wait Reset for Interrupt R/W R/W halted until a reset (Power On or Watch Dog). Notice, when writing to the processor status and control register, the run bit should always be written as a “1.” CY7C63413C CY7C63513C CY7C63613C Timer Timer Timer Bit 2 Bit 1 Bit ...
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... ZF are restored and interrupts are enabled when the RETI instruction is executed. Global Interrupt Enable Register 4 3 DAC Reserved Interrupt Enable R/W USB End Point Interrupt Enable Register 4 3 Reserved Reserved CY7C63413C CY7C63513C CY7C63613C 1.024-ms 128-µsec USB Bus RST Interrupt Interrupt Interrupt Enable Enable Enable R/W R/W R/W 2 ...
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... The USB Controller does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process. CY7C63413C CY7C63513C CY7C63613C Function Page [+] Feedback ...
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... In and Out), but must be placed in the correct mode to function as such. Also a non-Control endpoint can be made to act as a Control endpoint placed in a non appropriate mode. A ‘check’ Out token during a Status transaction checks to see that the Out is of zero length and has a Data Toggle (DTOG CY7C63413C CY7C63513C CY7C63613C Page [+] Feedback ...
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... ISR to unlock and get the mode register infor- mation. The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made during the previous transaction. CY7C63413C CY7C63513C CY7C63613C What the SIE does to Mode bits Interrupt? End Point Mode Re- ...
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... updates updates 1 updates updates updates CY7C63413C CY7C63513C CY7C63613C Set End Point Mode ACK response int ACK yes UC NoChange ignore yes UC NoChange ignore yes UC NoChange ignore no UC NoChange NAK yes UC NoChange NAK yes UC NoChange ignore no UC NoChange ignore no UC NoChange Stall yes ...
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... updates updates updates CY7C63413C CY7C63513C CY7C63613C Set End Point Mode ACK response int Stall yes ignore ignore Stall yes ACK yes UC NoChange ignore yes UC NoChange ignore yes UC NoChange ignore no UC NoChange NAK yes UC NoChange ignore no UC NoChange ignore no UC NoChange ignore ...
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... Ohms 45% 65 range, as well as DAC outputs. CC (2) is limited to minimize Ground-Drop noise effects. SS CY7C63413C CY7C63513C CY7C63613C +0.5V CC +0.5V CC [3] Conditions Non USB activity (note 4) USB activity (note 5.5V CC Oscillator off, D– > Voh min V = 5.0V, ceramic resonator CC Any pin Cumulative across all ports (note 6) Linear ramp ...
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... Measured at crossover point of differential data signals. 14. Limits total bus capacitance loading ( 400 pF per section 7.1.5 of revision 1.1 of USB specification. LOAD 15. DAC I/O Port not bonded out on CY7C63613C. See note on page 12 for firmware code needed for unused pins. Document #: 38-08027 Rev. *B Min. Max. ...
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... V crs V ol D− T PERIOD Differential Data Lines Document #: 38-08027 Rev CYC Figure 8. Clock Timing 90% 90% 10% 10% Figure 9. USB Data Signal Timing JR1 Consecutive Transitions PERIOD JR1 Paired Transitions PERIOD JR2 Figure 10. Receiver Jitter Tolerance CY7C63413C CY7C63513C CY7C63613C T JR2 Page [+] Feedback ...
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... Figure 11. Differential to EOP Transition Skew and EOP Width T PERIOD Differential Data Lines Ordering Information EPROM Ordering Code Size CY7C63413C-PVXC 8 KB CY7C63413C-PVXCT 8 KB CY7C63413C-PXC 8 KB CY7C63513C-PVXC 8 KB CY7C63613C-SXC 8 KB CY7C63413C-XC 8KB Document #: 38-08027 Rev. *B Crossover Point Extended + T PERIOD DEOP Crossover Points Consecutive Transitions PERIOD ...
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... Port0[6] 413.25 31 Port0[4] 98.00 30 Port0[2] 98.00 29 Port0[0] 98.00 28 DAC2 98.00 27 DAC0 98.00 26 XtalOut 98.00 25 XtalIn CY7C63413C CY7C63513C CY7C63613C X Y 1619.65 3023.60 1719.65 3023.60 1823.10 3023.60 1926.10 3023.60 2066.30 2657.35 2066.30 2554.35 2066.30 2451.35 2066.30 2348.35 2066.30 2245.35 2066.30 2142.35 2066.30 1130.35 2066 ...
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... Package Diagrams 48-Lead Shrunk Small Outline Package SP48 Document #: 38-08027 Rev. *B 40-Lead (600-Mil) Molded DIP P2 CY7C63413C CY7C63513C CY7C63613C 51-85061-*C 51-85019-*A Page [+] Feedback ...
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... MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE MIN. 3. DIMENSIONS IN INCHES MAX. 4. PACKAGE WEIGHT 0.65gms * 0.394[10.007] 0.419[10.642] SEATING PLANE 0.092[2.336] 0.105[2.667] 0.004[0.101] * CY7C63413C CY7C63513C CY7C63613C PART # S24.3 STANDARD PKG. SZ24.3 LEAD FREE PKG. * 0.0091[0.231] 0.015[0.381] 0.0125[0.317] 0.050[1.270] 51-85025-*C Page [+] Feedback ...
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... Document History Page Document Title: CY7C63413C, CY7C63513C, CY7C63613C Low-speed High I/O, 1.5 -Mbps USB Controller Document Number: 38-08027 Issue REV. ECN NO. Date ** 116224 06/12/02 *A 237148 SEE ECN *B 418699 See ECN Document #: 38-08027 Rev. *B Orig. of Change Description of Change DSG Change from Spec number: 38-00754 to 38-08027 ...