CY7C65620-56LFXAT Cypress Semiconductor Corp, CY7C65620-56LFXAT Datasheet - Page 9

• Manufacturer Part Number: CY7C65620-56LFXAT
• Description: CY7C65620-56LFXAT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65620-56LFXAT

• Lead Free Status / Rohs Status: Compliant

Pin Description
Table 3. Pin Assignments
Document Number: 38-08037 Rev. *T
Note
SPI Interface
Upstream Port
3. Unused port DD+/DD– lines can be left floating. Leave the port power, amber, and green LED pins unconnected, and deassert the overcurrent pin. Do not leave the
Pin
15
19
23
27
33
39
55
12
16
20
24
28
34
40
47
50
56
21
22
46
45
26
25
48
49
17
18
11
3
7
4
8
overcurrent pin floating; it is an input.
VBUSPOWER VBUSPOWER Input
CY7C65630
SELFPWR
SPI_SCK
RESET#
SPI_CS
SPI_SD
Name
XOUT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
XIN
D–
D+
[3]
CY7C65620
SELFPWR
SPI_SCK
RESET#
SPI_CS
SPI_SD
Name
XOUT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
XIN
D–
D+
Output
Output
Output
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Type Default
Input
Input
Input
I/O/Z
I/O/Z
I/O/Z
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
O
O
Z
Z
Z
V
V
V
V
V
V
V
V
V
V
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
24 MHz crystal IN or external clock input.
24 MHz crystal OUT. (NC if external clock is used)
Active LOW reset. This pin resets the entire chip. It is normally tied to
V
No other special power up procedure is required.
Self power. Indicator for bus or self powered. 0 is bus powered, 1 is self
powered.
VBUS. Connect to the VBUS pin of the upstream connector. This signal
indicates to the hub that it is in a connected state, and may enable the
D+ pull up resistor to indicate a connection. (The hub does so after the
external EEPROM is read).
SPI chip select. Connect to CS pin of the EEPROM.
SPI clock. Connect to EEPROM SCK pin.
SPI dataline connect to GND with 15 K
of the EEPROM.
Upstream D– Signal.
Upstream D+ Signal.
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
. This signal provides power to the chip.
. This signal provides power to the chip.
. This signal provides power to the chip.
. This signal provides power to the chip.
. This signal provides power to the chip.
. This signal provides power to the chip.
. This signal provides power to the chip.
. This signal provides power to the chip.
. This signal provides power to the chip.
. This signal provides power to the chip.
through a 100 K resistor, and to GND through a 0.1 µF capacitor.
Description
CY7C65620/CY7C65630

resistor and to the Data I/O pin
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