CY7C66113C-LTXC Cypress Semiconductor Corp, CY7C66113C-LTXC Datasheet - Page 22

• Manufacturer Part Number: CY7C66113C-LTXC
• Description: CY7C66113C-LTXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-LTXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Processor Series: CY7C66xx
• Core: M8
• Data Bus Width: 16 bit
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• Interface Type: HAPI, I2C, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 1
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

I
Internal hardware supports communication with external devices through two interfaces: a two wire I
1, 2, or 3 byte transfers. The I
this register are cleared on reset.
Bits [7,1:0] of the HAPI and I
the pin out configuration of the HAPI and I
interfaces. Bits [5:2] are used in HAPI mode only, and are
described in
Table 7
I
Table 7. HAPI Port Configuration
Table 8. I
I
The I
communication with external devices, supporting master, slave,
and multi-master modes of operation. The I
functions by handling the low level signaling in hardware, and
issuing interrupts as needed to allow firmware to take
appropriate action during transactions. While waiting for
firmware response, the hardware keeps the I
idle if necessary.
The I
microcontroller at the end of each received or transmitted byte,
when a stop bit is detected by the slave when in receive mode,
or when arbitration is lost. Details of the interrupt responses are
given in
The I
Data Register
Register
separate read and write registers. Generally, the I
Document Number: 38-08024 Rev. *D
Note
I
2
2
Bit #
Bit Name
Read/Write
Reset
2
3. I
2
C pin location configuration options. These I
C and HAPI Configuration Register
C Compatible Controller
C Configuration
2
C compatible function must be separately enabled.
2
2
2
C compatible interface consists of two registers, an I
C compatible interface generates an interrupt to the
I
C compatible block provides a versatile two wire
shows the HAPI port configurations, and
2
Hardware Assisted Parallel Interface
C Position (Bit 7,
(Figure
2
C Port Configuration
Port Width (Bit 0 and 1,
Hardware Assisted Parallel Interface
7
I
R/W
0
2
(Figure
C Position
Don’t Care
27). The Data Register is implemented as
0
1
14) and an I
Figure
2
2
6
Reserved
0
-
C compatible and HAPI functions, share a common configuration register (see
C Configuration Register control
11
10
01
00
25)
2
C Status and Control
Figure
Figure 25. HAPI/I
2
C compatible block
5
LEMPTY
Polarity
0
R/W
2
(HAPI).
C compatible bus
25)
2
2
Table 8
C compatible
2
C compatible
C Status and
I
2
C Port Width (Bit 1,
(HAPI).
shows
4
DRDY
Polarity
0
R/W
2
2
C
C Configuration Register
24 Bits: P3[7:0], P1[7:0], P0[7:0]
16 Bits: P1[7:0], P0[7:0]
8 Bits: P0[7:0]
No HAPI Interface
1
0
0
options exist due to pin limitations in certain packages, and to
allow simultaneous HAPI and I
HAPI operation is enabled whenever either HAPI Port Width Bit
(Bit 1 or 0) is non zero. This affects GPIO operation as described
in
compatible interface must be separately enabled.
Control Register are only monitored after the I
bits are valid at that time. Polling this register at other times could
read misleading bit status if a transaction is underway.
The I
port 2, and the I
1 or GPIO port 2. Refer to
for the bit definitions and functionality of the HAPI and
Configuration Register, which is used to set the locations of the
configurable I
enabled by setting bit 0 of the I
two LSB ([1:0]) of the corresponding GPIO port is placed in Open
Drain mode, regardless of the settings of the GPIO Configuration
Register. The electrical characteristics of the I
interface is the same as that of GPIO ports 1 and 2. Note that the
I
All control of the I
compatible block.
OL
Hardware Assisted Parallel Interface
(max) is 2 mA at V
2
3
Latch
Empty
R
0
Figure
C SCL clock is connected to bit 0 of GPIO port 1 or GPIO
25)
2
C pins. When the I
2
C SDA data is connected to bit 1 of GPIO port
2
CY7C66013C, CY7C66113C
C clock and data lines is performed by the I
2
Data
Ready
R
0
HAPI Port Width
I
I
I
OL
2
2
2
C on P2[1:0], 0:SCL, 1:SDA
C on P1[1:0], 0:SCL, 1:SDA
C on P2[1:0], 0:SCL, 1:SDA
= 2.0V for ports 1 and 2.
I
2
C and HAPI Configuration Register
2
2
C compatible operation.
C Status & Control Register, the
2
C compatible, and a HAPI for
2
1
HAPI Port
Width Bit 1
R/W
0
C compatible functionality is
I
2
C Position
Figure
ADDRESS 0x09
(HAPI). The I
2
C interrupt, as all
25)
2
Page 22 of 59
0
HAPI Port
Width Bit 0
R/W
0
C compatible
[3]
. All bits of
2
2
2
C
C
C
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