CY7C68053-56BAXIT Cypress Semiconductor Corp, CY7C68053-56BAXIT Datasheet - Page 36

• Manufacturer Part Number: CY7C68053-56BAXIT
• Description: CY7C68053-56BAXIT
• Manufacturer: Cypress Semiconductor Corp
• Series: MoBL-USB™r

Specifications of CY7C68053-56BAXIT

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB
• Number Of I /o: 56
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFBGA
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3687 - KIT DEV MOBL-USB FX2LP18
• Lead Free Status / Rohs Status: Details

9.13.4 Sequence Diagram of a Single and Burst Asynchronous Write
Figure 25
write in an asynchronous mode. The diagram shows a single
write followed by a burst write of 3 bytes and committing the
4-byte-short packet using PKTEND.
■
■
■
■
Document # 001-06120 Rev *J
At t = 0 the FIFO address is applied, ensuring that it meets the
setup time of t
(SLCS may be tied low in some applications).
At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of t
t
is asserted.
At t = 2, data must be present on the bus t
deasserting edge of SLWR.
At t = 3, deasserting SLWR causes the data to be written from
the data bus to the FIFO and then the FIFO pointer is
incremented. The FIFO flag is also updated after t
the deasserting edge of SLWR.
WRpwh
FIFOADR
PKTEND
FLAGS
SLWR
DATA
SLCS
. If the SLCS is used, it must be asserted before SLWR
illustrates the timing relationship of the SLAVE FIFO
t=0
SFA
WRpwl
t
SFA
. If SLCS is used, it must also be asserted
t =1
Figure 25. Slave FIFO Asynchronous Write Sequence and Timing Diagram
t
and minimum inactive pulse width of
WRpwl
t=2
t
SFD
t=3
N
t
t
FDH
WRpwh
t
FAH
t
XFLG
SFD
T=0
t
SFA
before the
T=1
XFLG
t
WRpwl
T=2
t
SFD
from
T=3
t
N+1
FDH
t
WRpwh
T=4
The same sequence of events is shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
Note In the burst write mode, once SLWR is deasserted, the data
is written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post
incremented.
In
SLWR is deasserted, the short 4-byte packet can be committed
to the host using the PKTEND. The external device must be
designed to not assert SLWR and the PKTEND signal at the
same time. It must be designed to assert the PKTEND after
SLWR is deasserted and meet the minimum deasserted pulse
width. The FIFOADDR lines are to be held constant during the
PKTEND assertion.
t
WRpwl
T=5
Figure 25
t
SFD
T=6
t
N+2
FDH
t
WRpwh
when the four bytes are written to the FIFO and
T=7
t
WRpwl
T=8
t
SFD
T=9
t
t
N+3
WRpwh
FDH
[16]
t
PEpwl
t
CY7C68053
XFLG
t
PEpwh
t
FAH
Page 36 of 42
[+] Feedback