CY8C3245AXI-158 Cypress Semiconductor Corp, CY8C3245AXI-158 Datasheet
CY8C3245AXI-158
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CY8C3245AXI-158 Summary of contents
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... AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus 2. This feature on select devices only. See Ordering Information 3. GPIOs with opamp outputs are not recommended for use with CapSense. Cypress Semiconductor Corporation Document Number: 001-56955 Rev. *H PRELIMINARY ® ...
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Contents 1. ARCHITECTURAL OVERVIEW ......................................... 3 2. PINOUTS ............................................................................. 5 3. PIN DESCRIPTIONS ......................................................... 10 4. CPU ................................................................................... 11 4.1 8051 CPU ................................................................. 11 4.2 Addressing Modes .................................................... 11 4.3 Instruction Set .......................................................... 12 4.4 DMA and PHUB ....................................................... 16 ...
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Architectural Overview Introducing the CY8C32 family of ultra low-power, flash Programmable System-on-Chip (PSoC PSoC 3 and 32-bit PSoC 5 platform. The CY8C32 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of ...
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In addition to the flexibility of the UDB array, PSoC also provides configurable digital blocks targeted at specific functions. For the CY8C32 family these blocks can include four 16-bit timers, 2 counters, and PWM blocks slave, master, and ...
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This enables the device to be powered directly from a single battery or solar cell. In addition, you can use the boost converter to generate other voltages required by the device, such as a 3.3-V supply for LCD glass drive. ...
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P2[6] (GPIO) P2[7] (GPIO, TMS, SWDIO) P1[0] (GPIO, TCK, SWDCK) P1[1] (GPIO, Configurable XRES) P1[2] (GPIO, TDO, SWV) P1[3] (GPIO, TDI) P1[4] (GPIO, nTRST) P1[5] Notes 7. The center pad on the QFN package should be connected to digital ...
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P2[6] (GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] Vssb Ind Vboost Vbat Vssd XRES (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (nTRST, GPIO) P1[5] ...
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P2[5] 1 (GPIO) P2[6] 2 (GPIO) P2[7] 3 (I2C0: SCL, SIO) P12[4] 4 (I2C0: SDA, SIO) P12[5] 5 (GPIO) P6[4] 6 (GPIO) P6[5] 7 (GPIO) P6[6] 8 (GPIO) P6[7] 9 Vssb 10 Ind 11 Vboost 12 Vbat 13 Vssd ...
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Figure 2-5. Example Schematic for 100-pin TQFP Part with Power Connections Vddd C6 0.1 uF Vssd 1 P2[5] 2 P2[6] 3 P2[7] 4 P12[4], SIO 5 P12[5], SIO 6 P6[4] 7 P6[5] 8 P6[6] 9 P6[7] 10 Vssb 11 Ind ...
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Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance Vssd Plane 3. Pin Descriptions IDAC0 Low resistance output pin for high current DAC (IDAC). Extref0, Extref1 External reference input to the analog system. GPIO General purpose ...
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USBIO, D+ Provides D+ connection directly to a USB 2.0 bus. May be used as a digital I/O pin. Pins are Do Not Use (DNU) on devices without USB. USBIO, D– Provides D– connection directly to a USB 2.0 bus. ...
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Instruction Set The 8051 instruction set is highly optimized for 8-bit handling and Boolean operations. The types of instructions supported include: Arithmetic instructions Logical instructions Data transfer instructions Boolean instructions Program branching instructions Table 4-1. Arithmetic Instructions Mnemonic ADD ...
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Logical Instructions The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. shows ...
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Data Transfer Instructions The data transfer instructions are of three types: the core RAM, xdata RAM, and the lookup tables. The core RAM transfer includes transfer between any two core RAM locations or SFRs. These instructions can use direct, ...
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Table 4-4. Boolean Instructions Mnemonic CLR C Clear carry CLR bit Clear direct bit SETB C Set carry SETB bit Set direct bit CPL C Complement carry CPL bit Complement direct bit ANL C, bit AND direct bit to carry ...
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Program Branching Instructions The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. shows the list of jump instructions. Table 4-5. Jump Instructions Mnemonic ACALL addr11 Absolute subroutine call LCALL ...
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Priority Levels The CPU always has higher priority than the DMA controller when their accesses require the same bus resources. Due to the system architecture, the CPU can never starve the DMA. DMA channels of higher priority (lower priority ...
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Interrupt Controller The interrupt controller provides a mechanism for hardware resources to change program execution to a new address, independent of the current task being executed by the main code. The interrupt controller provides enhanced features not found on ...
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Memory 5.1 Static RAM CY8C32 Static RAM (SRAM) is used for temporary data storage SRAM is provided and can be accessed by the 8051 or the DMA controller. See Memory Map Simultaneous access of ...
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Data, Address, and Control Signals PHUB Data, Address, and Control Signals Data, Address, and Control Signals 5.6 Memory Map The CY8C32 8051 memory map is very similar to the MCS-51 memory map. 5.6.1 Code Space The CY8C32 8051 code space ...
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SFRs The special function register (SFR) space provides access to frequently accessed registers. The memory map for the SFR memory space is shown in Table 5-2. Table 5-2. SFR Map Address 0/8 1/9 0×F8 SFRPRT15DR SFRPRT15PS 0×F0 B – ...
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Table 5-3. XDATA Data Address Map Address Range Purpose 0×00 0000 – 0×00 1FFF SRAM 0×00 4000 – 0×00 42FF Clocking, PLLs, and oscillators 0×00 4300 – 0×00 43FF Power management 0×00 4400 – 0×00 44FF Interrupt controller 0×00 4500 ...
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MHz 4-33 MHz IMO ECO 12-48 MHz Doubler Digital Clock Divider 16 bit Digital Clock Divider 16 bit 7 Digital Clock Divider 16 bit Digital Clock Divider 16 bit 6.1.1 Internal Oscillators 6.1.1.1 Internal Main Oscillator In most designs ...
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The 100-kHz clock (CLK100K) works as a low-power system clock to run the CPU. It can also generate time intervals such as fast sleep intervals using the fast timewheel. The fast timewheel is a 100-kHz, 5-bit counter clocked by the ...
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Each clock divider consists of an 8-input multiplexer, a 16-bit clock divider (divide by 2 and higher) that generates ~50 percent duty cycle clocks, system clock resynchronization logic, and deglitch logic. The outputs from each digital clock tree can be ...
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Power Modes PSoC 3 devices have four different power modes, as shown in Table 6-2 and Table 6-3. The power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing ...
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Figure 6-5. Power Mode Transitions Active Manual Sleep Alternate Active 6.2.1.1 Active Mode Active mode is the primary operating mode of the device. When in active mode, the active configuration template bits control which available resources are enabled or disabled. ...
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The switching frequency can be set to 100 kHz, 400 kHz, 2 MHz kHz to optimize efficiency and component cost. The 100 kHz, 400 kHz, and 2 MHz switching frequencies are generated using oscillators internal to the boost ...
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During sleep mode the regulators are periodically activated (buzzed) to provide supervisory services and to reduce wakeup time. At these times the PRES circuit is also buzzed to allow periodic voltage monitoring. ALVI, DLVI, AHVI – ...
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Additional features only provided on SIO pins: Higher drive strength than GPIO Hot swap capability (5 V tolerance at any operating V Programmable and regulated high input and output drive levels down to 1 analog input, CapSense, or ...
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Digital Input Path PRT[x]SIO_HYST_EN PRT[x]SIO_DIFF Reference Level PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Digital Input Path ...
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Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. drive modes. Table 6-6 shows the I/O pin’s drive ...
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High Impedance Analog The default reset state with both the output driver and digital input buffer turned off. This prevents any current from flowing in the I/O’s digital input buffer due to a floating voltage. This state is recommended for ...
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Analog Connections These connections apply only to GPIO pins. All GPIO pins may be used as analog inputs or outputs. The analog voltage present on the pin must not exceed the V supply voltage to which DDIO the GPIO ...
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Over Voltage Tolerance All I/O pins provide an over voltage tolerance feature at any operating There are no current limitations for the SIO pins as they present a high impedance load to the external circuit where ...
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Figure 7-1. CY8C32 Digital Programmable Architecture Digital Core System and Fixed Function Peripherals DSI Routing Interface UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB ...
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Document Number: 001-56955 Rev. *H PRELIMINARY ® PSoC 3: CY8C32 Family Datasheet Figure 7-2. PSoC Creator Framework Page 37 of 100 [+] Feedback ...
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Component Catalog Figure 7-3. Component Catalog The component catalog is a repository of reusable design elements that select device functionality and customize your PSoC device populated with an impressive selection of content; from simple primitives such as ...
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PSoC Creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. All steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity. ...
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Datapath Module The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band generators ...
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Independent of the ALU operation, these functions are available: Shift left Shift right Nibble swap Bitwise OR mask 7.2.2.3 Conditionals Each datapath has two compares, with bit masking options. Compare operands include the two accumulators and the two data registers ...
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Clock Generation Each subcomponent block of a UDB including the two PLDs, the datapath, and Status and Control, has a clock selection and control block. This promotes a fine granularity with respect to allocating clocking resources to UDB component ...
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Figure 7-13. Digital System Interconnect Tim ers Interrupt I2C C ounters C ontroller C ontroller D igital S ystem R outing I igital S ystem R outing I/F ...
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USB PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0 transceiver supporting all four USB transfer types: control, interrupt, bulk, and isochronous. PSoC Creator provides full configuration support. USB interfaces to hosts through two dedicated USBIO pins, which are ...
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I C features include: Slave and Master, Transmitter, and Receiver operation Byte processing for low CPU overhead Interrupt or polling CPU interface Support for bus speeds Mbps (3.4 Mbps in UDBs 10-bit addressing (10-bit ...
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Analog Routing The CY8C32 family of devices has a flexible analog routing architecture that provides the capability to connect GPIOs and different analog blocks, and also route signals between different analog blocks. One of the strong points of this ...
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ExVrefL ExVrefL1 GPIO P0[4] GPIO P0[5] GPIO * i0 P0[6] GPIO * P0[7] cmp0_vref (1.024V) GPIO cmp_muxvn[1:0] vref_cmp1 P4[2] cmp1_vref (0.256V) GPIO bg_vda_res_en Vdda Vdda/2 P4[3] refbuf_vref1 (1.024V) GPIO refbuf_vref2 (1.2V) P4[4] refsel[1:0] GPIO ...
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Analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. There are eight abus routes in CY8C32, four in the left half (abusl [0:3]) and four in the ...
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The ADC result is valid and available after the fourth conversion, at which time the EoC signal is generated. To detect the end of conversion, the system may poll a control register for status ...
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From Analog Routing 8.3.2 LUT The CY8C32 family of devices contains four LUTs. The LUT is a two input, one output lookup table that is driven by any one or two of the comparators in the chip. The output of ...
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CY8C32 family LCD driver system can drive a maximum of 736 segments. The PSoC LCD driver module was also designed with the conservative power budget of portable devices in mind, enabling different LCD ...
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DAC The CY8C32 parts contain a Digital to Analog Converter (DAC). The DAC is 8-bit and can be configured for either voltage or current output. The DAC supports CapSense, power supply regulation, and waveform generation. The DAC has the ...
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Table 9-1. Debug Configurations Debug and Trace Configuration SWV SWD + SWV 9.1 JTAG Interface The IEEE 1149.1 compliant JTAG interface exists on four or five pins (the nTRST pin is optional). The JTAG clock frequency can ...
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When the output is 1, the Write Once NV latch locks the part out of Debug and Test modes; it also permanently gates off the ability to erase or alter the contents of the latch. Matching ...
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Electrical Specifications Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, ...
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Device Level Specifications Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter Description V Analog supply voltage and input to DDA analog ...
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Table 11-2. DC Specifications (continued) Parameter Description [20] Sleep Mode CPU = OFF RTC = ON (= ECO32K ON, in low-power mode) Sleep timer = ON (= ILO ON at [21] 1 kHz) WDT = OFF Wake ...
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Table 11-3. AC Specifications Parameter Description F CPU frequency CPU F Bus frequency BUSCLK Svdd V ramp rate DD T Time from IO_INIT DDD DDA ≥ IPOR to I/O ports set to their reset states T ...
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Power Regulators Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description V Input voltage DDD V Output voltage ...
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Table 11-6. Inductive Boost Regulator DC Specifications (continued) Unless otherwise specified, operating conditions are µF || 0.1 µF BOOST Parameter Description V [25, 26] OUT Boost voltage range 1.8 V 1.9 V 2.0 V 2.4 V ...
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Inputs and Outputs Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.4.1 GPIO Table 11-1. GPIO DC Specifications Parameter Description V Input voltage high threshold IH V Input voltage low ...
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SIO Table 11-3. SIO DC Specifications Parameter Description Vinmax Maximum input voltage Vinref Input voltage reference (Differ- ential input mode) Output voltage reference (Regulated output mode) Voutref Input voltage high threshold V GPIO mode IH [28] Differential input mode ...
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Table 11-4. SIO AC Specifications (continued) Parameter Description SIO output operating frequency 3.3 V < V < 5.5 V, Unregu- DDIO lated output (GPIO) mode, fast strong drive mode 1.71 V < V < 3.3 V, Unregu- DDIO lated output ...
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Table 11-6. USBIO AC Specifications Parameter Description Tdrate Full-speed data rate average bit rate Tjr1 Receiver data jitter tolerance to next transition Tjr2 Receiver data jitter tolerance to pair transition Tdj1 Driver differential jitter to next transition Tdj2 Driver differential ...
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Analog Peripherals Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.5.1 Delta-sigma ADC Unless otherwise specified, operating conditions are: Operation in continuous sample mode fclk = 6.144 MHz Reference = ...
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Table 11-11. Delta-sigma ADC AC Specifications Parameter Description Startup time [33] THD Total harmonic distortion 12-Bit Resolution Mode SR12 Sample rate, continuous, high power BW12 Input bandwidth at max sample rate SINAD12int Signal to noise ratio, 12-bit, internal [33] reference ...
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Figure 11-11. Delta-sigma ADC Noise Histogram, 1000 sam- ples, 12-bit, 192 ksps, Int Ref REF 100.00 90.00 80.00 70.00 60.00 50.00 40.00 30.00 20.00 10.00 0.00 ADC counts ADC Counts 11.5.2 Voltage Reference Table 11-13. Voltage ...
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Comparator Table 11-15. Comparator DC Specifications Parameter Description Input offset voltage in fast mode V OS Input offset voltage in slow mode Input offset voltage in fast mode V OS Input offset voltage in slow mode V Input offset ...
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Table 11-17. IDAC DC Specifications (continued) Parameter Description Eg Gain error TC_Eg Temperature coefficient of gain error INL Integral nonlinearity DNL Differential nonlinearity Vcompliance Dropout voltage, source or sink mode I Operating current, code = 0 DD Document Number: 001-56955 ...
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Figure 11-12. IDAC INL vs Input Code, Range = 255 µA, Source Mode Figure 11-14. IDAC DNL vs Input Code, Range = 255 µA, Source Mode Figure 11-16. IDAC INL vs Temperature, Range = 255 µA, Fast Mode Document Number: ...
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Figure 11-18. IDAC Full Scale Error vs Temperature, Range = 255 µA, Source Mode Figure 11-20. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Source Mode Table 11-18. IDAC AC Specifications Parameter Description F Update rate ...
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Voltage Digital to Analog Converter (VDAC) See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-19. VDAC DC Specifications Parameter Description Resolution INL1 ...
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Figure 11-26. VDAC Full Scale Error vs Temperature Mode Figure 11-28. VDAC Operating Current vs Temperature, 1V Mode, Slow Mode Table 11-20. VDAC AC Specifications Parameter Description F Update rate DAC TsettleP Settling time to 0.1%, step 25% ...
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Temperature Sensor Table 11-21. Temperature Sensor Specifications Parameter Description Temp sensor accuracy 11.5.8 LCD Direct Drive Table 11-22. LCD Direct Drive DC Specifications Parameter Description I LCD system operating current CC I Current per segment driver CC_SEG V LCD ...
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Digital Peripherals Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.6.1 Timer The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; ...
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Pulse Width Modulation The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented in UDBs; for more information, see the PWM component datasheet in PSoC Creator.. Table 11-28. PWM DC Specifications Parameter ...
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USB Table 11-32. USB DC Specifications Parameter Description V Device supply for USB operation USB_5 V USB_3.3 V USB_3 11.6.6 Universal Digital Blocks (UDBs) PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, ...
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Memory Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.7.1 Flash Table 11-34. Flash DC Specifications Parameter Description Erase and program voltage Table 11-35. Flash AC Specifications Parameter Description T ...
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Table 11-39. NVL AC Specifications Parameter Description NVL endurance NVL data retention time 11.7.4 SRAM Table 11-40. SRAM DC Specifications Parameter Description V SRAM retention voltage SRAM Table 11-41. SRAM AC Specifications Parameter Description F SRAM operating frequency SRAM 11.7.5 ...
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Table 11-42. Asynchronous Read Cycle Specifications Parameter Description [38] T EMIF clock period Tcel EM_CEn low time Taddrv EM_CEn low to EM_Addr valid Taddrh Address hold time after EM_Wen high Toel EM_OEn low time Tdoesu Data to EM_OEn high setup ...
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EM_ Clock EM_ CEn EM_ Addr EM_ OEn EM_ Data EM_ ADSCn Table 11-44. Synchronous Read Cycle Specifications Parameter Description [39] T EMIF clock period Tcp/2 EM_Clock pulse high Tceld EM_CEn low to EM_Clock high Tcehd EM_Clock high to EM_CEn ...
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EM_ Clock EM_ CEn EM_ Addr EM_ WEn EM_ Data EM_ ADSCn Table 11-45. Synchronous Write Cycle Specifications Parameter Description [40] T EMIF clock Period Tcp/2 EM_Clock pulse high Tceld EM_CEn low to EM_Clock high Tcehd EM_Clock high to EM_CEn ...
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PSoC System Resources Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.8.1 POR with Brown Out For brown out detect in regulated mode, V mode. Table 11-46. Precise Power-on Reset ...
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Interrupt Controller Table 11-50. Interrupt Controller AC Specifications Parameter Description Delay from interrupt signal input to ISR code execution from ISR code 11.8.4 JTAG Interface Table 11-51. JTAG Interface AC Specifications Parameter Description f_TCK TCK frequency T_TDI_setup TDI setup ...
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Clocking Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.9.1 32 kHz External Crystal Table 11-54. 32 kHz External Crystal DC Specifications Parameter Description I Operating current CC CL External ...
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Internal Low-Speed Oscillator Table 11-58. ILO DC Specifications Parameter Description Operating current I CC Leakage current Table 11-59. ILO AC Specifications Parameter Description Startup time, all frequencies ILO frequencies (trimmed) 100 kHz 1 kHz F ILO ILO frequencies (untrimmed) ...
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Phase–Locked Loop Table 11-62. PLL DC Specifications Parameter Description I PLL operating current DD Table 11-63. PLL AC Specifications Parameter Description [43] Fpllin PLL input frequency PLL intermediate frequency [43] Fpllout PLL output frequency Lock time at startup [36] ...
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... Del-Sig CY8C3244AXI-159 0.5 ✔ 12-bit Del-Sig CY8C3244LTI-151 0.5 ✔ 12-bit Del-Sig CY8C3244LTI-161 0.5 ✔ 12-bit Del-Sig ✔ CY8C3244PVI-126 0.5 12-bit Del-Sig 32 KB Flash CY8C3245AXI-158 – 12-bit Del-Sig CY8C3245LTI-163 – 12-bit Del-Sig CY8C3245LTI-139 – 12-bit Del-Sig CY8C3245PVI-134 – 12-bit Del-Sig CY8C3245AXI-166 50 ...
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... Table 12-1. CY8C32 Family with Single Cycle 8051 (continued) MCU Core Part Number ✔ CY8C3245LTI-164 12-bit Del-Sig ✔ CY8C3245PVI-157 12-bit Del-Sig ✔ CY8C3245AXI-154 12-bit Del-Sig CY8C3245LTI-129 ✔ 12-bit Del-Sig CY8C3245LTI-160 ✔ 12-bit Del-Sig CY8C3245PVI-150 ✔ 12-bit Del-Sig 64 KB Flash CY8C3246AXI-137 50 64 ...
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Part Numbering Conventions PSoC 3 devices follow the part numbering convention described here. All fields are single character alphanumeric ( … …, Z) unless stated otherwise. CY8Cabcdefg-xxx a: Architecture 3: PSoC 3 5: PSoC ...
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Packaging Table 13-1. Package Characteristics Parameter Description T Operating ambient temperature A T Operating junction temperature J Package θJA (48-pin SSOP) Tja Package θJA (48-pin QFN) Tja Package θJA (68-pin QFN) Tja Package θJA (100-pin TQFP) Tja Package θJC ...
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Figure 13-1. 48-pin (300 mil) SSOP Package Outline 24 25 0.620 0.630 0.088 0.092 0.025 BSC TOP VIEW 7.00±0. PIN 1 DOT LASER MARK NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE ...
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Figure 13-3. 68-pin QFN 8×8 with 0.4 mm Pitch Package Outline (Sawn Version) TOP VIEW 8.000±0.100 PIN 1 DOT LASER MARK NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. ...
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Acronyms Table 14-1. Acronyms Used in this Document Acronym Description abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus archi- tecture) high-performance bus, an ARM data transfer bus ALU arithmetic logic unit AMUXBUS ...
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Table 14-1. Acronyms Used in this Document (continued) Acronym Description PGA programmable gain amplifier PHUB peripheral hub PHY physical layer PICU port interrupt control unit PLA programmable logic array PLD programmable logic device, see also PAL PLL phase-locked loop PMDD ...
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Document Conventions 16.1 Units of Measure Table 16-1. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohours kHz kilohertz kΩ kilohms ksps kilosamples ...
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Revision History ® Description Title: PSoC 3: CY8C32 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-56955 Submission Rev. ECN No. Date ** 2796903 11/04/09 *A 2824546 12/09/09 *B 2873322 02/04/10 Document Number: 001-56955 Rev. *H PRELIMINARY ® PSoC Orig. ...
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Description Title: PSoC 3: CY8C32 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-56955 *C 2903576 04/01/10 Document Number: 001-56955 Rev. *H PRELIMINARY ® PSoC MKEA Updated Vb pin in PCB Schematic. Updated Tstartup parameter in AC Specifications table. Added ...
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Description Title: PSoC 3: CY8C32 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-56955 *D 2938381 05/27/10 *E 2958674 06/22/10 *F 2989685 08/04/10 *G 3078568 11/04/10 *H 3107314 12/10/2010 Document Number: 001-56955 Rev. *H PRELIMINARY ® PSoC MKEA Replaced V ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...