CY8C3245PVI-157 Cypress Semiconductor Corp, CY8C3245PVI-157 Datasheet - Page 66

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CY8C3245PVI-157

Manufacturer Part Number
CY8C3245PVI-157
Description
CY8C3245PVI-157
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ 3 CY8C32xxr
Datasheet

Specifications of CY8C3245PVI-157

Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART
Peripherals
CapSense, DMA, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 5.5 V
Data Converters
A/D 2x12b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 11-3. AC Specifications
Document Number: 001-56955 Rev. *J
Note
F
F
Svdd
T
T
T
T
22. Based on device characterization (Not production tested).
STARTUP
SLEEP
IO_INIT
CPU
BUSCLK
HIBERNATE
Parameter
CPU frequency
Bus frequency
V
Time from V
≥ IPOR to I/O ports set to their reset
states
Time from V
≥ PRES to CPU executing code at
reset vector
Wakeup from sleep mode –
Application of non-LVD interrupt to
beginning of execution of next CPU
instruction
Wakeup from hibernate mode –
Application of external interrupt to
beginning of execution of next CPU
instruction
DD
ramp rate
Description
DDD
DDD
[22]
/V
/V
DDA
DDA
/V
/V
CCD
CCD
1.71 V
5.5 V
3.3 V
0.5 V
/V
/V
0 V
CCA
CCA
DC
Figure 11-4. F
1.71 V ≤ V
1.71 V ≤ V
V
V
boot mode (12 MHz typ.)
CCA
DDA
Valid Operating Region with SMP
/V
/V
CCD
DDD
Valid Operating Region
DDD
DDD
Conditions
, no PLL used, IMO
CPU Frequency
= regulated from
1 MHz
CPU
≤ 5.5 V
≤ 5.5 V
vs. V
DD
10 MHz
PSoC
50 MHz
Min
DC
DC
®
3: CY8C32 Family
Typ
Data Sheet
50.01
50.01
Max
100
10
66
15
Page 66 of 119
1
Units
MHz
MHz
V/ns
µs
µs
µs
µs
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