CY8C3246AXI-140 Cypress Semiconductor Corp, CY8C3246AXI-140 Datasheet - Page 32

• Manufacturer Part Number: CY8C3246AXI-140
• Description: CY8C3246AXI-140
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C32xxr

Specifications of CY8C3246AXI-140

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x12b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 6-5. Power Mode Transitions
6.2.1.1 Active Mode
Active mode is the primary operating mode of the device. When
in active mode, the active configuration template bits control
which available resources are enabled or disabled. When a
resource is disabled, the digital clocks are gated, analog bias
currents are disabled, and leakage currents are reduced as
appropriate. User firmware can dynamically control subsystem
power by setting and clearing bits in the active configuration
template. The CPU can disable itself, in which case the CPU is
automatically reenabled at the next wakeup event.
When a wakeup event occurs, the global mode is always
returned to active, and the CPU is automatically enabled,
regardless of its template settings. Active mode is the default
global power mode upon boot.
6.2.1.2 Alternate Active Mode
Alternate Active mode is very similar to Active mode. In alternate
active mode, fewer subsystems are enabled, to reduce power
consumption. One possible configuration is to turn off the CPU
and flash, and run peripherals at full speed.
6.2.1.3 Sleep Mode
Sleep mode reduces power consumption when a resume time of
15 µs is acceptable. The wake time is used to ensure that the
regulator outputs are stable enough to directly enter active
mode.
6.2.1.4 Hibernate Mode
In hibernate mode nearly all of the internal functions are
disabled. Internal voltages are reduced to the minimal level to
keep vital systems alive. Configuration state is preserved in
hibernate mode and SRAM memory is retained. GPIOs
configured as digital outputs maintain their previous values and
external GPIO pin interrupt settings are preserved. The device
can only return from hibernate mode in response to an external
I/O interrupt. The resume time from hibernate mode is less than
100 µs.
Document Number: 001-56955 Rev. *J
Manual
Buzz
Alternate
Active
Active
Sleep
Hibernate
6.2.1.5 Wakeup Events
Wakeup events are configurable and can come from an interrupt
or device reset. A wakeup event restores the system to active
mode. Firmware enabled interrupt sources include internally
generated interrupts, power supervisor, central timewheel, and
I/O interrupts. Internal interrupt sources can come from a variety
of peripherals, such as analog comparators and UDBs. The
central timewheel provides periodic interrupts to allow the
system to wake up, poll peripherals, or perform real-time
functions. Reset event sources include the external reset I/O pin
(XRES), WDT, and Precision Reset (PRES).
6.2.2 Boost Converter
Applications that use a supply voltage of less than 1.71 V, such
as solar or single cell battery supplies, may use the on-chip boost
converter. The boost converter may also be used in any system
that requires a higher operating voltage than the supply provides.
For instance, this includes driving 5.0 V LCD glass in a 3.3 V
system. The boost converter accepts an input voltage as low as
0.5 V. With one low cost inductor it produces a selectable output
voltage sourcing enough current to operate the PSoC and other
on-board components.
The boost converter accepts an input voltage from 0.5 V to 5.5 V
(V
provides a user configurable output voltage of 1.8 to 5.0 V
(V
than or equal to V
The block can deliver up to 50 mA (I
configuration.
Four pins are associated with the boost converter: V
V
V
inputs. An inductor is connected between the V
You can optimize the inductor value to increase the boost
converter efficiency based on input voltage, output voltage,
current and switching frequency. The External Schottky diode
shown in
V
Figure 6-6. Application for Boost Converter
BOOST
BOOST
BOOST
Vboost > 3.6 V
Schottky Diode
BAT
BOOST
Only required
Optional
), and can start up with V
, and Ind. The boosted output voltage is sensed at the
pin and must be connected directly to the chip’s supply
> 3.6 V.
). V
Figure 6-6
BAT
10 µH
22 µF
is typically less than V
BOOST
SMP
PSoC
is required only in cases when
Vbat
Vssb
Vboost
Ind
, then V
Vdda Vddd
BAT
®
PSoC
BOOST
3: CY8C32 Family
as low as 0.5 V. The converter
Vssa
Vssd
Vddio
BOOST
will be the same as V
BOOST
22 µF 0. 1 µF
) depending on
Data Sheet
; if V
BAT
Page 32 of 119
BAT
and Ind pins.
BAT
is greater
, V
SSB
BAT
,
.
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