CY8CTST200-24LQXIT Cypress Semiconductor Corp, CY8CTST200-24LQXIT Datasheet - Page 159
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CY8CTST200-24LQXIT
Manufacturer Part Number
CY8CTST200-24LQXIT
Description
CY8CTST200-24LQXIT
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200-24LQXIT
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
20
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-WQFN Exposed Pad, 24-HWQFN
Processor Series
CY8CTxx2xx
Core
M8C
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 18-11
to the point at which the RX Buffer register is loaded with the received byte. This means that to send a byte in the next trans-
fer, it must be loaded into the TX Buffer register before the falling edge of SS_. This ensures a minimum setup time for the
first bit, since the leading edge of the first SCLK must latch in the received data. If SS_ is not toggled between each byte or is
forced low through the configuration register, the leading edge of SCLK is used to define the start of transfer. However, in this
case, the user must provide the required setup time (one-half clock minimum before the leading edge) with a knowledge of
system latencies and response times.
Figure 18-12
edge of the first SCLK to the point at which the RX Buffer register is loaded with the received byte. Loading the shifter by the
leading edge of the clock has the effect of providing the required one-half clock setup time, as the data is latched into the
receiver on the trailing edge of the SCLK in these modes.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
SS Forced Low
SS
SCLK (Mode 0)
SCLK (Mode 1)
SS Toggled on a Message Basis
SS
SCLK (Mode 0)
SCLK (Mode 1)
SS Toggled on Each Byte
SS
SCLK (Mode 0)
SCLK (Mode 1)
illustrates TX data loading in modes 0 and 1. A transfer in progress is defined to be from the falling edge of SS_
illustrates TX data loading in modes 2 and 3. In this case, a transfer in progress is defined to be from the leading
SCLK (Mode 2)
SCLK (Mode 3)
Transfer in Progress
Transfer in Progress
Transfer in Progress
Figure 18-11. Mode 0 and 1 Transfer in Progress
Figure 18-12. Mode 2 and 3 Transfer in Progress
(No Dependance on SS)
Transfer in Progress
Transfer in Progress
Transfer in Progress
159
SPI
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