CY8CTST200-24LQXIT Cypress Semiconductor Corp, CY8CTST200-24LQXIT Datasheet - Page 163
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CY8CTST200-24LQXIT
Manufacturer Part Number
CY8CTST200-24LQXIT
Description
CY8CTST200-24LQXIT
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200-24LQXIT
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
20
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-WQFN Exposed Pad, 24-HWQFN
Processor Series
CY8CTxx2xx
Core
M8C
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19.2
The following registers are associated with the Programmable Timer and are listed in address order. The register descriptions
have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are
reserved bits and are not detailed in the register descriptions that follow. Reserved bits must always be written with a value of
‘0’. For a complete table of programmable timer registers, refer to the
page
19.2.1
The
(PT0_CFG) configures the PSoC’s programmable timer.
Bit 2: CLKSEL. This bit determines if the timer runs on the
32 kHz clock or CPU clock. If the bit is set to 1'b1, the timer
runs on the CPU clock, otherwise, the timer runs on the 32
kHz clock.
Bit 1: One Shot. This bit determines if the timer runs in
one-shot mode or continuous mode. In one-shot mode the
timer completes one full count cycle and terminates. Upon
termination, the START bit in this register is cleared. In con-
tinuous mode, the timer reloads the count value each time
upon completion of its count cycle and repeats.
19.2.2
The
(PT1_CFG) configures the PSoC’s programmable timer.
Bit 2: CLKSEL. This bit determines if the timer runs on the
32 kHz clock or CPU clock. If the bit is set to 1'b1, the timer
runs on the CPU clock, otherwise, the timer runs on the 32
kHz clock.
Bit 1: One Shot. This bit determines if the timer runs in
one-shot mode or continuous mode. In one-shot mode the
timer completes one full count cycle and terminates. Upon
termination, the START bit in this register is cleared. In con-
tinuous mode, the timer reloads the count value each time
upon completion of its count cycle and repeats.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
0,B0h
0,B3h
Address
Address
106.
Programmable
Programmable
Register Definitions
PT0_CFG
PT1_CFG
PT0_CFG Register
PT1_CFG Register
Name
Name
Timer
Timer
Bit 7
Bit 7
Configuration
Configuration
Bit 6
Bit 6
Bit 5
Bit 5
Register
Register
Bit 4
Bit 4
Bit 0: START. This bit starts the timer counting from a full
count. The full count is determined by the value loaded into
the data registers. This bit is cleared when the timer is run-
ning in one-shot mode upon completion of a full count cycle.
For additional information, refer to the
page
Bit 0: START. This bit starts the timer counting from a full
count. The full count is determined by the value loaded into
the data registers. This bit is cleared when the timer is run-
ning in one-shot mode upon completion of a full count cycle.
For additional information, refer to the
page
221.
224.
Summary Table of the System Resource Registers on
Bit 3
Bit 3
CLKSEL
CLKSEL
Bit 2
Bit 2
One Shot
One Shot
Bit 1
Bit 1
PT0_CFG register on
PT1_CFG register on
Programmable Timer
START
START
Bit 0
Bit 0
Access
Access
RW : 0
RW : 0
163
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