CYD18S72V-100BBI Cypress Semiconductor Corp, CYD18S72V-100BBI Datasheet
CYD18S72V-100BBI
Specifications of CYD18S72V-100BBI
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CYD18S72V-100BBI Summary of contents
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... JTAG for boundary scan, and asynchronous Master Reset (MRST). The CYD18S72V device have limited features. Please see Table 3 on page 6 Seamless Migration to Next-Generation Dual-Port Family Cypress offers a migration path for all devices to the next-gener- ation devices in the Dual-Port family with a compatible footprint ...
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... CNTRST L Counter Logic RET L CNTINT WRP L Mailboxes INT L Note 1. CYD04S72V have 16 address bits, CYD09S72V have 17 address bits and CYD18S72V have 18 bits. Document Number : 38-06069 Rev. *K CONFIG Block IO Control Control Dual-Ported Array Arbitration Logic Address & Counter Logic INT R JTAG RESET READY ...
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... Leave this ball unconnected for 128K x 72 and 64K x72 configurations. 8. These balls are not applicable for CYD18S72V device. They need to be tied to VDDIO. 9. These balls are not applicable for CYD18S72V device. They need to be tied to VSS. 10. These balls are not applicable for CYD18S72V device. They need connected. ...
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... Port External High-Speed IO Reference Input. Port IO Power Supply. Reserved pins for future features. Master Reset Input. MRST is an asynchronous input signal and affects both ports. A master reset operation is required at power-up. JTAG Reset Input. CYD04S72V CYD09S72V CYD18S72V is L Page [+] Feedback ...
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... Left Port CE A INT R/W L 0L–17L L L 3FFFF 3FFFE HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK 1 CYD04S72V CYD09S72V CYD18S72V Right Port CE A INT R R 0R–17R 3FFFF 3FFFE 1.5 CORE Page LOW. R [+] Feedback ...
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... Counter operation and mask register operation is independent of chip enables. 17. The CYD04S72V has 16 address bits and a maximum address value of FFFF. The CYD09S72V has 17 address bits and a maximum address value of 1FFFF. The CYD18S72V has 18 address bits and a maximum address value of 3FFFF. Document Number : 38-06069 Rev. *K ...
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... This even-odd address scheme stores one half of the 144-bit data in even memory locations, and the other half in odd memory locations. CYD04S72V CYD09S72V CYD18S72V n n – –2. From Page ...
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... Figure 1. Counter, Mask, and Mirror Logic Block Diagram Document Number : 38-06069 Rev. *K Mask Register Counter/ Address Register Load/Increment Mirror Counter Increment Logic Wrap 17 Bit 0 +1 Wrap 1 Detect CYD04S72V CYD09S72V CYD18S72V Address RAM Decode Array To Readback and Address Decode 17 Wrap To Counter [1] Page [+] Feedback ...
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... Boundary Scan Hierarchy for FLEx72 Family Internally, the CYD04S72V and CYD09S72V have two DIEs while CYD18S72V have four DIEs. Each DIE contains all the circuitry required to support boundary scan testing. The circuitry includes the TAP, TAP controller, instruction register, and data registers ...
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... Document Number : 38-06069 Rev. *K TDO Figure 3. Scan Chain Value 0h Reserved for version number C002h Defines Cypress DIE number for CYD18S72V and CYD09S72V C001h Defines Cypress DIE number for CYD04S72V 034h Allows unique identification of FLEx72 family device vendor 1 Indicates the presence register Description Captures the Input/Output ring contents ...
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... CYD09S72V CYD04S72V 160 210 CYD09S72V 224 320 CYD18S72V = Max CYD04S72V CYD09S72V CYD18S72V Ambient CORE Temperature 0°C to +70°C 3.3 V ± 165 mV 1.8 V ± 100 mV –40°C to +85°C 3.3 V ± 165 mV 1.8 V ± 100mV –133 –100 Unit Typ Max Min Typ Max 2 ...
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... CYD04S72V CYD09S72V CYD18S72V Max Unit 20 pF [25 3 590 435 10% < –100 CYD18S72V CYD18S72V Unit Min. Max Min. Max 133 100 MHz 7 3.4 4.5 ns 3.4 4.5 ns 2.0 3.0 ns 2.0 3.0 ns 2.2 2.7 ns 1.0 1 ...
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... NA 0.5 5.0 0.5 5.7 NA 5.2 6.0 5.7 5.0 5.0 5.0 6.0 6.0 6.0 5.0 5.0 5.0 10.0 10.0 10.0 10.0 CYD04S72V CYD09S72V CYD18S72V –100 CYD18S72V Unit Max Min. Max 5.5 5 5.5 0 5.5 ns 5.0 5.2 ns ...
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... Test Clock TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document Number : 38-06069 Rev. *K Description TMSS t TMSH t TDIS t TDIH t TDOX t TDOV CYD04S72V CYD09S72V CYD18S72V CYD04S72V CYD09S72V CYD18S72V Unit –167/–133/–100 Min. Max 10 MHz 100 TCYC Page [+] Feedback ...
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... Numbers are for reference only. Document Number : 38-06069 Rev. *K ACTIVE t CL2 A A n+1 n+2 t CD2 CKLZ following the next rising edge of the clock. IH with CNT/MSK = V constantly loads the address on the rising edge of the CLK CYD04S72V CYD09S72V CYD18S72V n n+1 n+2 t OHZ t OLZ t OE Page [+] Feedback ...
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... One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK. Document Number : 38-06069 Rev CD2 HC CD2 SC CKHZ CKLZ [32, 35, 36, 37, 38 n+1 n+2 n CD2 DC t CKHZ OPERATION CYD04S72V CYD09S72V CYD18S72V CD2 CKHZ CKLZ CD2 CKHZ CD2 CKLZ A A n+2 n n+2 WRITE Page (B1) [+] Feedback ...
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... Document Number : 38-06069 Rev. *K [32, 35, 37, 38 n+1 n+2 n n+2 n+3 t CD2 OHZ WRITE [37 SAD t t SCN t CD2 n+1 COUNTER HOLD READ WITH COUNTER CYD04S72V CYD09S72V CYD18S72V A A n+4 n+5 t CD2 Q READ HAD HCN Q Q n+2 READ WITH COUNTER Page n+4 n+3 [+] Feedback ...
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... ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN D D DATA WRITE EXTERNAL ADDRESS Document Number : 38-06069 Rev. *K [38 n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD CYD04S72V CYD09S72V CYD18S72V n+2 n+3 n n+3 n+4 WRITE WITH COUNTER Page [+] Feedback ...
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... BE0 – BE7 = LOW MRST = CNT/MSK = HIGH 40. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. Document Number : 38-06069 Rev CD2 CKLZ READ READ ADDRESS 0 ADDRESS 1 ADDRESS A CYD04S72V CYD09S72V CYD18S72V CD2 READ READ ADDRESS A m ...
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... the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document Number : 38-06069 Rev. *K [41, 42, 43, 44 CA2 CM2 n+1 n CD2 CKHZ CKLZ INCREMENT in next clock cycle. CKLZ . CKHZ CYD04S72V CYD09S72V CYD18S72V A A n+4 n n+1 n+2 n+3 Page [+] Feedback ...
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... Document Number : 38-06069 Rev. *K [45, 46, 47 CKLZ t CCS CD2 CNTRST = MRST = CNT/MSK = HIGH. 1 CYC2 CYD04S72V CYD09S72V CYD18S72V violated, indeterminate data will be Read out. CCS + t ) after the rising edge of R_Port's clock. CYC2 CD2 + t ) after the rising edge of R_Port's clock. CD2 Page [+] Feedback ...
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... Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock. Document Number : 38-06069 Rev. *K 1FFFE 1FFFF t t RCINT SCINT SINT t RINT 3FFFF m+1 CYD04S72V CYD09S72V CYD18S72V Last_Loaded Last_Loaded + n+2 n m+3 m+4 Page [+] Feedback ...
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... Speed Ordering Code (MHz) 256K × 72 (18-Mbit) 3.3 V Synchronous CYD18S72V Dual-Port SRAM 133 CYD18S72V-133BBC CYD18S72V-133BBI 100 CYD18S72V-100BBC CYD18S72V-100BBI 128K × 72 (9-Mbit) 3.3 V Synchronous CYD09S72V Dual-Port SRAM 133 CYD09S72V-133BBC 64K x 72 (4-Mbit) 3.3 V Synchronous CYD04S72V Dual-Port SRAM 167 CYD04S72V-167BBC Ordering Code Definitions CY ...
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... Package Diagram Document Number : 38-06069 Rev. *K CYD04S72V CYD09S72V CYD18S72V 51-85124 *G Page [+] Feedback ...
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... Document History Page Document Title: CYD04S72V / CYD09S72V / CYD18S72V FLEx72™ 3 K/128 K/256 K × 72 Synchronous Dual-Port RAM Document Number: 38-06069 Orig. of REV. ECN NO. Issue Date Change ** 125859 06/17/03 *A 128707 08/01/03 *B 128997 09/18/03 *C 129936 09/30/03 *D 233830 See ECN *E 288892 See ECN *F 327355 See ECN ...
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... The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number : 38-06069 Rev. *K cypress.com/go/plc Revised December 15, 2010 CYD04S72V CYD09S72V CYD18S72V PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 ...