DSPIC30F2010-20E/SO Microchip Technology, DSPIC30F2010-20E/SO Datasheet - Page 129

• Manufacturer Part Number: DSPIC30F2010-20E/SO
• Description: IC,DSP,16-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.3.1.1
The oscillator start-up circuitry is not linked to the POR
circuitry. Some crystal circuits (especially low fre-
quency crystals) will have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after the POR timer and the PWRT have
expired:
• The oscillator circuit has not begun to oscillate.
• The oscillator start-up timer has NOT expired (if a
• The PLL has not achieved a LOCK (if PLL is
If the FSCM is enabled and one of the above conditions
is true, then a clock failure trap will occur. The device
will automatically switch to the FRC oscillator and the
user can switch to the desired crystal oscillator in the
trap ISR.
19.3.1.2
If the FSCM is disabled and the Power-up Timer
(PWRT) is also disabled, then the device will exit rap-
idly from Reset on power-up. If the clock source is
FRC, LPRC, EXTRC, or EC, it will be active
immediately.
If the FSCM is disabled and the system clock has not
started, the device will be in a frozen state at the Reset
vector until the system clock starts. From the user’s
perspective, the device will appear to be in Reset until
a system clock is available.
19.3.2
The BOR module is based on an internal voltage refer-
ence circuit. The main purpose of the BOR module is to
generate a device Reset when a brown-out condition
occurs. Brown-out conditions are generally caused by
glitches on the AC mains (i.e., missing portions of the
AC cycle waveform due to bad power transmission
lines or voltage sags due to excessive current draw
when a large inductive load is turned on).
The BOR module allows selection of one of the
following voltage trip points:
• 2.6V-2.71V
• 4.1V-4.4V
• 4.58V-4.73V
© 2011 Microchip Technology Inc.
crystal oscillator is used).
used).
Note:
BOR: PROGRAMMABLE
BROWN-OUT RESET
The BOR voltage trip points indicated here
are nominal values provided for design
guidance only.
POR with Long Crystal Start-up Time
(with FSCM Enabled)
Operating without FSCM and PWRT
A BOR will generate a Reset pulse which will reset the
device. The BOR will select the clock source, based on
the device Configuration bit values (FOS<1:0> and
FPR<3:0>). Furthermore, if an Oscillator mode is
selected, the BOR will activate the Oscillator Start-up
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock will be held
until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the POR time-out (T
time-out (T
Reset is released. If T
is being used, then a nominal delay of T
is applied. The total delay in this case is (T
T
The BOR status bit (RCON<1>) will be set to indicate
that a BOR has occurred. The BOR circuit, if enabled,
will continue to operate while in Sleep or Idle modes
and will reset the device should V
threshold voltage.
FIGURE 19-6:
FSCM
Note:
Note 1: External Power-on Reset circuit is
).
2: R should be suitably chosen so as to
3: R1 should be suitably chosen so as to
PWRT
Dedicated supervisory devices, such as
the MCP1XX and MCP8XX, may also be
used as an external Power-on Reset
circuit.
required only if the V
is too slow. The diode D helps discharge
the capacitor quickly when V
down.
make sure that the voltage drop across
R does not violate the device’s electrical
specification.
limit any current flowing into MCLR from
external capacitor C, in the event of
MCLR/V
trostatic Discharge (ESD) or Electrical
Overstress (EOS).
D
V
) will be applied before the internal
dsPIC30F2010
DD
R
C
PP
PWRT
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
pin breakdown due to Elec-
R1
= 0 and a crystal oscillator
DD
DD
DD
POR
dsPIC30F
MCLR
POWER-UP)
DS70118J-page 129
fall below the BOR
power-up slope
) and the PWRT
FSCM
DD
powers
= 100 μs
POR
+