DSPIC33FJ12MC201-E/P Microchip Technology, DSPIC33FJ12MC201-E/P Datasheet - Page 177

• Manufacturer Part Number: DSPIC33FJ12MC201-E/P
• Description: 12 KB Flash, 1 KB RAM, 40 MIPS, 13 I/O, 16-bit Motor Control DSC, NanoWatt 20 PD
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC201-E/P

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.0
The Inter-Integrated Circuit™ (I
complete hardware support for both Slave and Multi-
Master modes of the I
standard, with a 16-bit interface.
The I
• The SCLx pin is clock
• The SDAx pin is data
The I
• I
• I
• I
• I
• Serial clock synchronization for I
• I
© 2009 Microchip Technology Inc.
Note:
modes of operation.
master and slaves
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
collision and arbitrates accordingly
2
2
2
2
2
C interface supporting both Master and Slave
C Slave mode supports 7-bit and 10-bit addresses
C Master mode supports 7-bit and 10-bit addresses
C port allows bidirectional transfers between
C supports multi-master operation, detects bus
2
2
C module has a 2-pin interface:
C module offers the following key features:
INTER-INTEGRATED CIRCUIT™
(I
2
This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual”, Section 19. “Inter-
Integrated Circuit™ (I
which is available on the Microchip web
site (www.microchip.com).
C™)
2
C serial communication
reference
2
C™) module provides
2
2
C™)” (DS70195),
C port can be
source.
Preliminary
To
dsPIC33FJ12MC201/202
18.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7-bit and 10-bit addressing.
The I
master on an I
The following types of I
• I
• I
• I
For details about the communication sequence in each
of these modes, refer to the Microchip web site
(www.microchip.com) for the latest “dsPIC33F Family
Reference Manual” sections.
18.2
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write:
• I2CxRSR is the shift register used for shifting data
• I2CxRCV is the receive buffer and the register to
• I2CxTRN is the transmit register to which bytes
• I2CxADD register holds the slave address
• ADD10 status bit indicates 10-bit Address mode
• I2CxBRG acts as the Baud Rate Generator (BRG)
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
which data bytes are written, or from which data
bytes are read
are written during a transmit operation
reload value
2
2
2
C slave operation with 7-bit address
C slave operation with 10-bit address
C master operation with 7-bit or 10-bit address
2
C module can operate either as a slave or a
Operating Modes
I
2
C Registers
2
C bus.
2
C Standard and Fast mode
2
C operation are supported:
DS70265D-page 175