DSPIC33FJ16GP304T-I/PT Microchip Technology, DSPIC33FJ16GP304T-I/PT Datasheet - Page 155
![16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 TQFP 10x10x1mm T/R](/photos/6/82/68251/c04-076_pt_sml.jpg)
DSPIC33FJ16GP304T-I/PT
Manufacturer Part Number
DSPIC33FJ16GP304T-I/PT
Description
16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
2.DSPIC33FJ16GP304-IPT.pdf
(284 pages)
3.DSPIC33FJ16GP304-IPT.pdf
(8 pages)
4.DSPIC33FJ16GP304-IPT.pdf
(14 pages)
Specifications of DSPIC33FJ16GP304T-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ16GP304T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ16GP304T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ12MC201-ISO PDF datasheet
- DSPIC33FJ16GP304-IPT PDF datasheet #2
- DSPIC33FJ16GP304-IPT PDF datasheet #3
- DSPIC33FJ16GP304-IPT PDF datasheet #4
- Current page: 155 of 284
- Download datasheet (4Mb)
16.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and
Multi-Master modes of the I
standard, with a 16-bit interface.
The I
• The SCLx pin is clock
• The SDAx pin is data
The I
• I
• I
• I
• I
• Serial clock synchronization for I
• I
© 2011 Microchip Technology Inc.
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
modes of operation
addressing
addressing
master and slaves
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
collision and arbitrates accordingly
2
2
2
2
2
Note 1: This data sheet summarizes the features
C interface supporting both Master and Slave
C Slave mode supports 7-bit and 10-bit
C Master mode supports 7-bit and 10-bit
C port allows bidirectional transfers between
C supports multi-master operation, detects bus
2
2
C module has a 2-pin interface:
C module offers the following key features:
2: Some registers and associated bits
INTER-INTEGRATED
CIRCUIT™ (I
of the dsPIC33FJ32GP202/204 and
dsPIC33FJ16GP304 family of devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 19. “Inter-Integrated Circuit™
(I
PIC24H Family Reference Manual”,
which is available on the Microchip
website (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
2
C™)” (DS70195) of the “dsPIC33F/
2
C™)
2
C serial communication
2
C) module provides
2
C port can be
in
16.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7-bit and 10-bit addressing.
The I
master on an I
The following types of I
• I
• I
• I
For details about the communication sequence in each
of these modes, refer to the “dsPIC33F/PIC24H Family
Reference Manual”.
16.2
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
• I2CxRSR is the shift register used for shifting
• I2CxRCV is the receive buffer and the register to
• I2CxTRN is the transmit register to which bytes
• The I2CxADD register holds the slave address.
• A status bit, ADD10, indicates 10-bit Address
• I2CxBRG acts as the Baud Rate Generator
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
data.
which data bytes are written, or from which data
bytes are read.
are written during a transmit operation.
mode.
(BRG) reload value.
2
2
2
C slave operation with 7-bit addressing
C slave operation with 10-bit addressing
C master operation with 7-bit or 10-bit addressing
2
C module can operate either as a slave or a
Operating Modes
I
2
C Registers
2
C bus.
2
C Standard and Fast mode
2
C operation are supported:
DS70290G-page 155
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