DSPIC33FJ16GP304T-I/PT Microchip Technology, DSPIC33FJ16GP304T-I/PT Datasheet - Page 67
![16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 TQFP 10x10x1mm T/R](/photos/6/82/68251/c04-076_pt_sml.jpg)
DSPIC33FJ16GP304T-I/PT
Manufacturer Part Number
DSPIC33FJ16GP304T-I/PT
Description
16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
2.DSPIC33FJ16GP304-IPT.pdf
(284 pages)
3.DSPIC33FJ16GP304-IPT.pdf
(8 pages)
4.DSPIC33FJ16GP304-IPT.pdf
(14 pages)
Specifications of DSPIC33FJ16GP304T-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ16GP304T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ16GP304T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ12MC201-ISO PDF datasheet
- DSPIC33FJ16GP304-IPT PDF datasheet #2
- DSPIC33FJ16GP304-IPT PDF datasheet #3
- DSPIC33FJ16GP304-IPT PDF datasheet #4
- Current page: 67 of 284
- Download datasheet (4Mb)
FIGURE 6-2:
© 2011 Microchip Technology Inc.
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
Oscillator Clock
Device Status
POR Reset
BOR Reset
Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is
SYSRST
FSCM
V
DD
2: BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user
6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock
active until V
the V
becomes stable.
period of time (T
at the appropriate level for full-speed operation. After the delay T
inactive, which in turn enables the selected oscillator to start generating clock cycles.
Table
application programs a GOTO instruction at the reset address, which redirects program execution to the
appropriate start-up routine.
is ready and the delay T
1
SYSTEM RESET TIMING
BOR
6-1. Refer to
2
threshold and the delay T
DD
T
crosses the V
PWRT
V
POR
POR
Section 8.0 “Oscillator Configuration”
) after a BOR. The delay T
FSCM
POR
elapsed.
threshold and the delay T
Vbor
V
BOR
BOR
has elapsed. The delay T
T
PWRT
T
3
BOR
Reset
Time
PWRT
ensures that the system power supplies have stabilized
T
OSCD
POR
for more information.
has elapsed.
PWRT
BOR
T
OST
4
ensures the voltage regulator output
has elapsed, the SYSRST becomes
T
LOCK
DS70290G-page 67
5
6
Run
DD
T
FSCM
crosses
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