DSPIC33FJ16MC102-I/SP Microchip Technology, DSPIC33FJ16MC102-I/SP Datasheet - Page 160

• Manufacturer Part Number: DSPIC33FJ16MC102-I/SP
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SPDIP .300in TU
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC102-I/SP

• Processor Series: dsPIC33F
• Core: dsPIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Interface Type: SPI, I2C, UART, JTAG
• Number Of Programmable I/os: 35
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 16KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Rohs Compliant: Yes
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 21
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Details

dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
REGISTER 15-5:
DS70652C-page 160
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-11
bit 10-8
bit 7
bit 6-4
bit 3
bit 2-0
Note 1:
U-0
U-0
—
—
The PWMxCON1 register is a write-protected register. Refer to
Registers”
Unimplemented: Read as ‘0’
PMOD3:PMOD1: PWM I/O Pair Mode bits
1 = PWM I/O pin pair is in the Independent PWM Output mode
0 = PWM I/O pin pair is in the Complementary Output mode
Unimplemented: Read as ‘0’
PEN3H:PEN1H: PWMxH I/O Enable bits
1 = PWMxH pin is enabled for PWM output
0 = PWMxH pin disabled, I/O pin becomes general purpose I/O
Unimplemented: Read as ‘0’
PEN3L:PEN1L: PWMxL I/O Enable bits
1 = PWMxL pin is enabled for PWM output
0 = PWMxL pin disabled, I/O pin becomes general purpose I/O
PEN3H
R/W-0
U-0
—
PWMxCON1: PWM CONTROL REGISTER 1
for more information on the unlock sequence.
W = Writable bit
‘1’ = Bit is set
PEN2H
R/W-0
U-0
—
PEN1H
R/W-0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
(1)
Section 15.3 “Write-protected
PMOD3
PEN3L
R/W-0
R/W-0
© 2011 Microchip Technology Inc.
x = Bit is unknown
PMOD2
PEN2L
R/W-0
R/W-0
PMOD1
PEN1L
R/W-0
R/W-0
bit 8
bit 0