DSPIC33FJ32GP202T-I/SO Microchip Technology, DSPIC33FJ32GP202T-I/SO Datasheet - Page 185

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DSPIC33FJ32GP202T-I/SO

Manufacturer Part Number
DSPIC33FJ32GP202T-I/SO
Description
16-bit DSC, 32KB Flash,40 MIPS,nanoWatt 28 SOIC .300in T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ32GP202T-I/SO

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ32GP202T-I/SOTR
TABLE 19-2:
© 2011 Microchip Technology Inc.
WDTPOST<3:0>
POSCMD<1:0>
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
FCKSM<1:0>
FPWRT<2:0>
OSCIOFNC
IOL1WAY
WDTPRE
FWDTEN
ICS<1:0>
Bit Field
JTAGEN
WINDIS
ALTI2C
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 CONFIGURATION BITS
DESCRIPTION (CONTINUED)
Register
FOSC
FOSC
FOSC
FOSC
FWDT
FWDT
FWDT
FWDT
FPOR
FPOR
FICD
FICD
Immediate Clock Switching Mode bits
Immediate Peripheral Pin Select Configuration
Immediate OSC2 Pin Function bit (except in XT and HS modes)
Immediate Primary Oscillator Mode Select bits
Immediate Watchdog Timer Enable bit
Immediate Watchdog Timer Window Enable bit
Immediate Watchdog Timer Prescaler bit
Immediate Watchdog Timer Postscaler bits
Immediate Alternate I
Immediate Power-on Reset Timer Value Select bits
Immediate JTAG Enable bit
Immediate ICD Communication Channel Select bits
Effect
RTSP
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
1 = Allow only one re-configuration
0 = Allow multiple re-configurations
1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
11 = Primary oscillator disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled.
0 = Watchdog Timer enabled/disabled by user software (LPRC can be
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
1 = 1:128
0 = 1:32
1111 = 1:32,768
1110 = 1:16,384
0001 = 1:2
0000 = 1:1
1 = I
0 = I
111 = PWRT = 128 ms
110 = PWRT = 64 ms
101 = PWRT = 32 ms
100 = PWRT = 16 ms
011 = PWRT = 8 ms
010 = PWRT = 4 ms
001 = PWRT = 2 ms
000 = PWRT = Disabled
1 = JTAG enabled
0 = JTAG disabled
11 = Communicate on PGEC1 and PGED1
10 = Communicate on PGEC2 and PGED2
01 = Communicate on PGEC3 and PGED3
00 = Reserved, do not use
.
.
.
2
2
Clearing the SWDTEN bit in the RCON register will have no effect.)
disabled by clearing the SWDTEN bit in the RCON register)
C mapped to SDA1/SCL1 pins
C mapped to ASDA1/ASCL1 pins
2
C pins
Description
DS70290G-page 185

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