DSPIC33FJ32GP202T-I/SO Microchip Technology, DSPIC33FJ32GP202T-I/SO Datasheet - Page 20

• Manufacturer Part Number: DSPIC33FJ32GP202T-I/SO
• Description: 16-bit DSC, 32KB Flash,40 MIPS,nanoWatt 28 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32GP202T-I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC33FJ32GP202T-I/SOTR

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
3.3
The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
features a 17-bit by 17-bit single-cycle multiplier that is
shared by both the MCU ALU and DSP engine. The mul-
tiplier can perform signed, unsigned and mixed-sign mul-
tiplication. Using a 17-bit by 17-bit multiplier for 16-bit by
16-bit multiplication not only allows you to perform
mixed-sign multiplication, it also achieves accurate results
for special operations, such as (-1.0) x (-1.0).
FIGURE 3-1:
DS70290G-page 20
PSV and Table
Control Block
Data Access
Program Memory
Address Latch
Data Latch
Special MCU Features
23
23
Controller
Interrupt
23
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 CPU CORE BLOCK DIAGRAM
to Various Blocks
Control Signals
Control
Decode and
Instruction
Stack
Logic
PCU
Program Counter
Control
24
8
PCH
Control
Logic
Loop
16
PCL
16
Y Data Bus
X Data Bus
Divide Support
DSP Engine
Instruction Reg
Data Latch
ROM Latch
Address
Address Generator Units
X RAM
Latch
16
16
The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
supports 16/16 and 32/16 divide operations, both frac-
tional and integer. All divide instructions are iterative oper-
ations. They must be executed within a REPEAT loop,
resulting in a total execution time of 19 instruction cycles.
The divide operation can be interrupted during any of
those 19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit left
or right shift in a single cycle. The barrel shifter can be
used by both MCU and DSP instructions.
Data Latch
Address
Y RAM
Latch
EA MUX
W Register Array
16
16
16
16 x 16
16
16-bit ALU
© 2011 Microchip Technology Inc.
16
16
To Peripheral Modules
16
16