EP2SGX90EF1152I4 Altera, EP2SGX90EF1152I4 Datasheet - Page 52

• Manufacturer Part Number: EP2SGX90EF1152I4
• Description: Stratix II GX
• Manufacturer: Altera

Specifications of EP2SGX90EF1152I4

• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Not Compliant

Logic Array Blocks
Logic Array
Blocks
2–44
Stratix II GX Device Handbook, Volume 1
EP2SGX30
EP2SGX60
EP2SGX90
EP2SGX130
Table 2–17. Stratix II GX Device Resources
Device
Columns/Blocks
M512 RAM
6/202
7/329
8/488
9/699
Applications and Protocols Supported with Stratix II GX Devices
Each Stratix II GX transceiver block is designed to operate at any serial bit
rate from 600 Mbps to 6.375 Gbps per channel. The wide data rate range
allows Stratix II GX transceivers to support a wide variety of standards
and protocols, such as PCI Express, GIGE, SONET/SDH, SDI, OIF-CEI,
and XAUI. Stratix II GX devices are ideal for many high-speed
communication applications, such as high-speed backplanes,
chip-to-chip bridges, and high-speed serial communications links.
Example Applications Support for Stratix II GX
Stratix II GX devices can be used for many applications, including:
■
■
Each logic array block (LAB) consists of eight adaptive logic modules
(ALMs), carry chains, shared arithmetic chains, LAB control signals, local
interconnects, and register chain connection lines. The local interconnect
transfers signals between ALMs in the same LAB. Register chain
connections transfer the output of an ALM register to the adjacent ALM
register in a LAB. The Quartus II Compiler places associated logic in a
LAB or adjacent LABs, allowing the use of local, shared arithmetic chain,
and register chain connections for performance and area efficiency.
Table 2–17
Stratix II GX LAB structure.
Traffic management with various levels of quality of service (QoS)
and integrated serial backplane interconnect
Multi-port single-protocol switching (for example, PCI Express,
GIGE, XAUI switch, or SONET/SDH)
Columns/Blocks
M4K RAM
4/144
5/255
6/408
7/609
shows Stratix II GX device resources.
M-RAM
Blocks
1
2
4
6
Columns/Blocks
DSP Block
2/16
3/36
3/48
3/63
Figure 2–32
Columns
LAB
49
62
71
81
Altera Corporation
October 2007
shows the
LAB Rows
36
51
68
87