EVAL-AD5292EBZ Analog Devices Inc, EVAL-AD5292EBZ Datasheet - Page 22

• Manufacturer Part Number: EVAL-AD5292EBZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5292EBZ

• Main Purpose: Digital Potentiometer
• Embedded: Yes
• Utilized Ic / Part: AD5292
• Primary Attributes: 1 Channel, 256 Position
• Secondary Attributes: SPI Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5291/AD5292
THEORY OF OPERATION
The AD5291 and AD5292 digital potentiometers are designed to
operate as true variable resistors for analog signals that remain
within the terminal voltage range of V
patented ±1% resistor tolerance feature helps to minimize the total
RDAC resistance error, which reduces the overall system error
by offering better absolute matching and improved open-loop
performance. The digital potentiometer wiper position is
determined by the RDAC register contents. The RDAC register
acts as a scratchpad register, allowing as many value changes as
necessary to place the potentiometer wiper in the correct
position. The RDAC register can be programmed with any
position setting using the standard SPI interface by loading the
16-bit data-word. Once a desirable position is found, this value
can be stored in a 20-TP memory register. Thereafter, the wiper
position is always restored to that position for subsequent power-
up. The storing of 20-TP data takes approximately 6 ms; during
this time, the shift register is locked, preventing any changes from
taking place. The RDY pin identifies the completion of this 20-
TP storage.
SERIAL DATA INTERFACE
The AD5291 and AD5292 contain a serial interface ( SYNC ,
SCLK, DIN and SDO) that is compatible with SPI interface
standards, as well as most DSPs. The part allows writing of data
via the serial interface to every register.
SHIFT REGISTER
The AD5291 and AD5292 shift register is 16 bits wide (see
Figure 2). The 16-bit input word consists of two unused bits
(set to 0), followed by four control bits, and 10 RDAC data bits.
Table 11. Command Operation Truth Table
Command
0
1
2
3
4
5
6
7
8
1
2
X = don’t care.
In the AD5291, this bit is a don’t care.
C3
0
0
0
0
0
0
0
0
1
Command Bits [DB13:DB10]
C2
0
0
0
0
1
1
1
1
0
C1
0
0
1
1
0
0
1
1
0
C0
0
1
0
1
0
1
0
1
0
SS
< V
TERM
D9
X
D9
X
X
X
X
X
X
X
< V
X
D8
X
X
X
X
X
X
D8
X
DD
. The
D7
X
D7
X
X
X
X
X
X
X
D6
X
D6
X
X
X
X
X
X
X
Rev. D | Page 22 of 32
Data Bits [DB9:DB0]
D5
X
D5
X
X
X
X
X
X
X
D4
D4
X
X
X
X
D4
X
X
X
For the AD5291, the lower two RDAC data bits are don’t cares if
the RDAC register is read from or written to. Data is loaded MSB
first (Bit DB15). The four control bits determine the function of
the software command (see Table 11). Figure 3 shows a timing
diagram of a typical AD5291 and AD5292 write sequence.
The write sequence begins by bringing the SYNC line low. The
SYNC pin must be held low until the complete data-word is
loaded from the DIN pin. When SYNC returns high, the serial
data-word is decoded according to the commands in
The command bits (Cx) control the operation of the digital
potentiometer. The data bits (Dx) are the values that are loaded
into the decoded register. The AD5291 and AD5292 have an
internal counter that counts a multiple of 16 bits (a frame) for
proper operation. For example, AD5291 and AD5292 work with
a 32-bit word but does not work properly with a 31-bit or 33-bit
word. The AD5291 and AD5292 do not require a continuous
SCLK, when
be operated at close to the V
power consumption in the digital input buffers.
RDAC REGISTER
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with all zeros, the wiper is connected to Terminal B of
the variable resistor. The RDAC register is a standard logic register;
there is no restriction on the number of changes allowed.
D3
D3
X
X
D3
D3
X
X
X
X
1
D2
X
D2
X
X
D2
D2
X
X
X
SYNC is high, and all serial interface pins should
D1
X
D1
X
X
X
D1
D1
X
X
2
D0
X
D0
X
X
X
D0
D0
X
D0
2
LOGIC
Operation
Write contents of serial data to RDAC.
output in the next frame.
to 20-TP memory.
value.
Read contents of 20-TP memory, or
status of 20-TP memory, from the SDO
output in the next frame.
Write contents of serial data to control
register.
Read control register from the SDO
output in the next frame.
D0 = 0 (normal mode).
D0 = 1 (device placed in shutdown mode).
NOP command: do nothing.
Read RDAC wiper setting from the SDO
Store wiper setting: store RDAC setting
Reset: refresh RDAC with 20-TP stored
Software shutdown.
supply rails to minimize
Table 11
.