KSZ8851-16MLLI Micrel Inc, KSZ8851-16MLLI Datasheet - Page 54

• Manufacturer Part Number: KSZ8851-16MLLI
• Description: 10/100BT Ethernet MAC + PHY With Generic (8, 16-bit) Bus Interface (I-Temp)
• Manufacturer: Micrel Inc

Specifications of KSZ8851-16MLLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3505

0x88 – 0x8B: Reserved
RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR
This register is used to program the received frame duration timer threshold.
RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR
This register is used to program the received data byte count threshold.
Interrupt Enable Register (0x90 – 0x91): IER
This register enables the interrupts from the QMU and other sources.
August 2009
Micrel, Inc.
13
12
11
10-0
Bit
15-0
Bit
15-0
Bit
15
14
-
0x0
0x0
0x0
0x0
0x000
Default Value
0x0000
Default Value
0x0000
Default Value
RO
RW
WO
(Read
back is
“0”)
WO
R/W
RW
R/W
RW
R/W
RW
RW
the data register. The increment is by one for every byte access, by two for every word
access, and by four for every double word access.
When this bit is reset, the RX frame data pointer is manually controlled by user to access
the RX frame location.
Reserved.
WST Write Sample Time
This bit is used to select the WRN active to write data valid time as shown in Figure 11.
0: WRN active to write data valid sample time is range of 8nS (min) to 16nS (max).
1: WRN active to write data valid sample time is 4nS (max).
EMS Endian Mode Selection
This bit is used to select either Big or Little Endian mode when Endian mode select
strapping pin (10) is NC or tied to GND.
0: is set to Little Endian Mode
1: is set to Big Endian Mode
RXFP RX Frame Pointer
RX Frame data pointer index to the Data register for access.
This pointer value must reset to 0x000 before each DMA operation from the host CPU to
read RXQ frame buffer.
Description
RXDTT Receive Duration Timer Threshold
To program received frame duration timer threshold value in 1us interval. The maximum
value is 0xCFFF.
When bit 7 set to 1 in RXQCR register, the KSZ8851-16MLL will set RX interrupt (bit 13 in
ISR) after the time starts at first received frame in RXQ buffer and exceeds the threshold
set in this register.
Description
RXDBCT Receive Data Byte Count Threshold
To program received data byte threshold value in byte count.
When bit 6 set to 1 in RXQCR register, the KSZ8851-16MLL will set RX interrupt (bit 13 in
ISR) when the number of received bytes in RXQ buffer exceeds the threshold set in this
register.
Description
LCIE Link Change Interrupt Enable
When this bit is set, the link change interrupt is enabled.
When this bit is reset, the link change interrupt is disabled.
TXIE Transmit Interrupt Enable
When this bit is set, the transmit interrupt is enabled.
When this bit is reset, the transmit interrupt is disabled.
54
KSZ8851-16MLL/MLLI
M9999-083109-2.0