ADUM3472CRSZ Analog Devices Inc, ADUM3472CRSZ Datasheet - Page 6

• Manufacturer Part Number: ADUM3472CRSZ
• Description: ISOLAT DGTL 2.5KVRMS 4CH 20SSOP
• Manufacturer: Analog Devices Inc
• Series: iCoupler®r

Specifications of ADUM3472CRSZ

• Operating Temperature: -40°C ~ 105°C
• Inputs - Side 1/side 2: 2/2
• Number Of Channels: 4
• Isolation Rating: 2500Vrms
• Voltage - Supply: 3.3V, 5V
• Data Rate: 25Mbps
• Propagation Delay: 60ns
• Output Type: Logic
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• No. Of Channels: 4
• Supply Current: 33mA
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +105°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Parameter
AC SPECIFICATIONS
1
2
3
4
The contributions of supply current values for all four channels are combined at identical data rates.
The V
current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as
described in the
The power demands of the quiescent operation of the data channels was not separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
This current is available for driving external loads at the V
capacitive load representing the maximum dynamic load conditions. Refer to the
maximum data rate.
ADuM347xARWZ
ADuM347xCRWZ
Refresh Rate
Logic High Output Voltages
Logic Low Output Voltages
Channel-to-Channel Matching,
Minimum Pulse Width
Minimum Pulse Width
Propagation Delay Skew
Channel-to-Channel Matching,
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
Common-Mode Transient Immunity
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
ISO
Change vs. Temperature
Codirectional Channels
Opposing Directional Channels
at Logic High Output
at Logic Low Output
supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional
Power Consumption
PLH
PLH
− t
− t
section. The dynamic I/O channel load must be treated as an external load and included in the V
PHL
PHL
|
|
Symbol
PWD
PW
PWD
V
V
V
V
PW
t
t
t
t
t
t
t
t
|CM
|CM
f
PHL
PSK
PSKCD
PHL
PSK
PSKCD
PSKOD
R
r
OAH
OCH
OAL
OCL
/t
, t
, t
F
, V
, V
H
L
, V
, V
|
/t
|
PLH
PLH
OBL
ODL
ISO
OBH
ODH
PSKOD
,
output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full
,
Min
V
V
1
25
30
25
25
CC
CC
− 0.2, V
− 0.5, V
Rev. 0 | Page 6 of 32
ISO
1SO
− 0.2
− 0.5
Power Consumption
Typ
5.0
4.8
0.0
0.0
60
60
5
2.5
35
35
1.0
Max
0.1
0.4
1000
100
40
50
50
40
75
8
45
8
15
section for calculation of available current at less than the
Unit
V
V
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kV/μs
kV/μs
Mbps
Mbps
ps/°C
Mbps
Test Conditions/Comments
C
I
I
I
I
C
C
C
C
C
C
C
C
C
C
C
C
C
C
V
transient magnitude = 800 V
V
transient magnitude = 800 V
Ox
Ox
Ox
Ox
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Ix
Ix
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= −20 μA, V
= −4 mA, V
= 20 μA, V
= 4 mA, V
= V
= 0 V, V = 1000 V,
DD
or V
ISO
Ix
ISO
Ix
Ix
= V
power budget.
Ix
= V
, V
= V
= V
CM
IxL
IxL
IxH
IxH
= 1000 V,