AD9866BCPRL Analog Devices Inc, AD9866BCPRL Datasheet - Page 19
![IC FRONT-END MIXED-SGNL 64-LFCSP](/photos/6/50/65021/505-64-lfcsp_sml.jpg)
AD9866BCPRL
Manufacturer Part Number
AD9866BCPRL
Description
IC FRONT-END MIXED-SGNL 64-LFCSP
Manufacturer
Analog Devices Inc
Datasheet
1.AD9866-EB.pdf
(48 pages)
Specifications of AD9866BCPRL
Rohs Status
RoHS non-compliant
Rf Type
HPNA, VDSL
Features
12-bit ADC(s), 12-bit DAC(s)
Package / Case
64-VFQFN, CSP Exposed Pad
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3/3.135V
Operating Supply Voltage (max)
3.6/3.465V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Package Type
LFCSP
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Not Compliant
SERIAL PORT
Table 10. SPI Register Mapping
Address
(Hex)
SPI PORT CONFIGURATION AND SOFTWARE RESET
0x00
POWER CONTROL REGISTERS (via PWR_DWN pin)
0x01
0x02
HALF-DUPLEX POWER CONTROL
0x03
PLL CLOCK MULTIPLIER/SYNTHESIZER CONTROL
0x04
0x05
0x06
Rx PATH CONTROL
0x07
1
Bit
Break-
down
(7)
(6)
(5)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
(7:3)
(2)
(1)
(0)
(5)
(4)
(3:2)
(1:0)
(2)
(1)
(0)
(7:6)
(5)
(4)
(3:2)
(1)
(0)
(5)
(4)
(0)
Description
4-Wire SPI
LSB First
S/W Reset
Clock Syn.
TxDAC/IAMP
Tx Digital
REF
ADC CML
ADC
PGA Bias
RxPGA
CLK Syn.
TxDAC/IAMP
Tx Digital
REF
ADC CML
ADC
PGA Bias
RxPGA
Tx OFF Delay
Rx _TXEN
Tx PWRDN
Rx PWRDN
Duty Cycle Enable
f
PLL Divide-N
PLL Multiplier-M
OSCIN to RXCLK
Invert RXCLK
Disabled RXCLK
CLKOUT2 Divide
CLKOUT2 Invert
CLKOUT2 Disable
CLKOUT1 Divide
CLKOUT1 Invert
CLKOUT1 Disable
Initiate Offset Cal.
Rx Low Power
Rx Filter ON
ADC
from PLL
Width
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
1
1
1
1
1
2
2
1
1
1
2
1
1
2
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0xFF
0
0
00
01
0
0
0
01
0
01
0
0
0
0
1
CONFIG = 0
MODE = 0 (Half-Duplex)
Rev. A | Page 19 of 48
Power-Up Default Value
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0xFF
0
0
00
10*
0
0
0
01
0
0
01
0
0
0
1*
1
CONFIG = 1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
N/A
0
0
00
01
0
0
0
01
0
0
01
0
0
0
0
1
CONFIG = 0
MODE = 1 (Full-Duplex)
0
0
0
0
0
0
0
0
0
0
0
1*
1
1
1
1
1
1
1
N/A
0
0
00
01
1*
0
0
01
0
1*
01
0
1*
0
1*
1
CONFIG = 1
Comments
Default SPI configuration is
3-wire, MSB first.
PWR_DWN = 0.
Default setting is for all
blocks powered on.
PWR_DWN = 1.
Default setting* is for all
functional blocks powered
down except PLL.
*MODE = CONFIG = 1.
Setting has PLL powered
down with OSCIN input
routed to RXCLK output.
Default setting is for TXEN
input to control power
on/off of Tx/Rx path.
Tx driver delayed by 31
1/f
Default setting is Duty Cycle
Restore disabled, ADC CLK
from OSCIN input, and PLL
multiplier × 2 setting.
*PLL multiplier × 4 setting.
Full-duplex RXCLK normally
at nibble rate.
*Exception on power-up.
Default setting is CLKOUT2
and CLKOUT1 enabled with
divide-by-2.
*CLKOUT1 and CLKOUT2
disabled.
Default setting has LPF ON
and Rx path at nominal
power bias setting.
*Rx path to low power.
DATA
clock cycles.
AD9866