AD9866BCPRL Analog Devices Inc, AD9866BCPRL Datasheet - Page 31

• Manufacturer Part Number: AD9866BCPRL
• Description: IC FRONT-END MIXED-SGNL 64-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9866BCPRL

• Rohs Status: RoHS non-compliant
• Rf Type: HPNA, VDSL
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-VFQFN, CSP Exposed Pad
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Supply Voltage (max): 3.6/3.465V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: LFCSP
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

outputs left open for optimum linearity performance. The
transformer
current, I
signal independent, a series resistor (not shown) can be inserted
between AVDD and the transformer’s center-tap to reduce the
IAMP’s common-mode voltage, V
dissipation on the IC. The V
the power dissipated in the IAMP alone is as follows:
A step-down transformer
increase the output power, P_OUT, delivered to the load. This
causes the output load, R
differential output by T
swing seen at the IAMP’s output. For example, the IAMP can
deliver 24 dBm of peak power to a 50 Ω load, if a 1.41:1 step-
down transformer is used. This results in 5 V p-p voltage swings
appearing at IOUTN+ and IOUTN− pins. Figure 42 shows how
the third order intercept point, OIP3, of the IAMP varies as a
function of common-mode voltage over a 2.5 MHz to 20.0 MHz
span with a 2-tone signal having a peak power of approximately
24 dBm with IOUT
For applications requiring an IOUT
secondary’s path to deliver the additional current to the load.
IOUTG+ and IOUTN+ should be shorted as well as IOUTG−
and IOUTN−. If IOUT
delivered to the load, then the current gain in the secondary
path, G, can be set by the following equation:
The linearity performance becomes limited by the secondary
mirror path’s distortion.
1
0.1µF
The B6080 and BX6090 transformers from Pulse Engineering are worthy of
consideration for current and voltage modes.
P
G = IOUT
IAMP
TxDAC
0 TO –7.5dB
BIAS
R
= 2 × (N + G) × I × V
SET
1
, drawn by the IAMP. Also, because I
should be specified to handle the dc standing
PK
/12.5 – 4
Figure 64. Current-Mode Operation
PK
0 TO –12dB
= 50 mA.
PK
2
, resulting in a larger differential voltage
L
1
represents the peak current to be
, to be reflected back to the IAMP’s
IAMP
with a turn ratio, T, can be used to
CM
bias should not exceed 5.0 V and
IOUTG–
CM
IOUTN+
IOUTG+
IOUTN–
CM
PK
, and reduce the power
exceeding 50 mA, set the
0.1µF
IOUT
P_OUT
IOUT
PK
PK
PK
= (N+G) × 1
AVDD
= (IOUT
I
BIAS
T:1
BIAS
PK
= 2 × (N+G) × 1
remains
)
2
× T
R
2
L
× R
L
Rev. A | Page 31 of 48
(2)
(3)
IAMP VOLTAGE-MODE OPERATION
The voltage-mode configuration is shown in Figure 65. This
configuration is suited for applications having a poorly defined
load that can vary over a considerable range. A low impedance
voltage driver can be realized with the addition of two external
RF bipolar npn transistors (Phillips PBR951) and resistors. In
this configuration, the current mirrors in the primary path
(IOUTN outputs) feed into scaling resistors, R, generating a
differential voltage into the bases of the npn transistors. These
transistors are configured as source followers with the secon-
dary path current mirrors appearing at IOUTG+ and IOUTG−
providing a signal-dependent bias current. Note that the
IOUTP outputs must remain open for proper operation.
The peak differential voltage signal developed across the npn’s
bases is as follows:
where:
N is the gain setting of the primary mirror.
I is the standing current of the TxDAC defined in Equation 1.
The common-mode bias voltage seen at IOUTN+ and IOUTN−
is approximately AVDD − VOUT
voltage seen at IOUTG+ and IOUTG− is approximately the
npn’s V
the voltage-mode configuration, the total power dissipated
within the IAMP is as follows:
The emitters of the npn transistors are ac-coupled to the trans-
former
to 2 Ω. Note that protection diodes are not shown for clarity
purposes, but should be considered if interfacing to a power or
phone line.
The amount of standing and signal-dependent current used to
bias the npn transistors depends on the peak current, IOUT
required by the load. If the load is variable, determine the worst
case, IOUT
0.1µF
VOUT
P
+ (AVDD − VOUT
TxDAC
IAMP
1
BE
0 TO –7.5dB
via a 0.1 µF blocking capacitor and series resistor of 1 Ω
R
drop below this level (AVDD − VOUT
SET
= 2 × I {(AVDD − VOUT
PK
PK
, and add 3 mA of margin to ensure that the npn
= R × (N × I)
Figure 65. Voltage-Mode Operation
0 TO –12dB
IAMP
PK
− 0.65) × G}
IOUTG–
IOUTN+
IOUTG+
IOUTN–
IOUT
PK
PK
R
, while the common-mode
PK
) × N
R
AVDD
AVDD
DUAL NPN
PHILLIPS PBR951
R
R
S
S
PK
0.1µF
0.1µF
− 0.65). In
AD9866
TO LOAD
PK
(4)
(5)
,