MT9M413C36STM Aptina LLC, MT9M413C36STM Datasheet - Page 9

• Manufacturer Part Number: MT9M413C36STM
• Description: SENSOR IMAGE MONO CMOS 280-PGA
• Manufacturer: Aptina LLC
• Type: CMOS Imagingr

Specifications of MT9M413C36STM

• Pixel Size: 12µm x 12µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 500
• Voltage - Supply: 3.3V
• Package / Case: 280-PGA
• Sensor Image Color Type: Monochrome
• Sensor Image Size: 1280x1024Pixels
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -5C to 60C
• Package Type: CPGA
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 280
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1153

CAL_STRT_N
pulse that initiates the ADC calibration sequence. The
pulse must not be actuated for 1 microsecond after
either power-up or removal of the sensor from a
power-down state. Users may find it easiest to cali-
brate by means of the logic reset.
CAL_DONE_N
output pulse that is asserted when the ADC calibration
is complete. The device will automatically initiate a
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MT9M413C36STC.fm - Ver. 3.0 1/04 EN
CAL_STRT_N is a two-clock cycle-wide active-low
CAL_DONE_N is a two-clock cycle-wide active-low
Figure 8: Typical I/O Signal Timing (Initialization Sequence)
CAL_DONE_N
CAL_DONE_N
CAL_STRT_N
SYSCLK
SYSCLK
LRST_N
1.3-MEGAPIXEL CMOS ACTIVE-PIXEL
9
calibration sequence upon a logic reset. Completion of
this sequence, in cases where it is initiated by a reset, is
still with the CAL_DONE_N signal. This process is
complete within 112 SYSCLK cycles of CAL_STRT_N.
This process is complete within 112 SYSCLK cycles of
LRST_N.
LRST_N
that resets the digital logic. It puts all logic into a
known state (all flip-flops are reset). This signal also
initiates an ADC calibration sequence.
LRST_N is a two-clock cycle-wide active-low pulse
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DIGITAL IMAGE SENSOR
©2004 Micron Technology, Inc. All rights reserved.