CYII4SM6600AB-QDC Cypress Semiconductor Corp, CYII4SM6600AB-QDC Datasheet - Page 25

• Manufacturer Part Number: CYII4SM6600AB-QDC
• Description: SENSOR IMAGE MONO CMOS 68-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM6600AB-QDC

• Package / Case: 68-LCC
• Pixel Size: 3.5µm x 3.5µm
• Active Pixel Array: 2210H x 3002V
• Frames Per Second: 5
• Voltage - Supply: 2.5V, 3.3V
• Operating Supply Voltage: 2.5 V to 3.3 V
• Maximum Operating Temperature: + 65 C
• Minimum Operating Temperature: - 30 C
• Image Size: 2210 H x 3002 V
• Color Sensing: Black/White
• Sensor Image Color Type: Monochrome
• Sensor Image Size Range: >= 480,000Pixels
• Sensor Image Size: 2210x3002Pixels
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 3.3V
• Operating Temp Range: -30C to 65C
• Package Type: CLCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package: 68CLCC
• Operating Temperature: -30 to 65 °C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Pixel Output Timing
Using Two Analog Outputs
The pixel signal at the OUT1 (OUT2) output becomes valid after
four SYS_CLOCK cycles when the internal X_SYNC (equal to
start of PIXEL_VALID output) appears (see
PIXEL_VALID and EOL/EOF pulses can be delayed by the user
through the DELAY register.
T1: Row blanking time (see
T2: 4 SYS_CLOCK cycles.
Document Number: 001-02366 Rev. *G
Table 12
Figure 25. Pixel Output Timing Multiplexing to One Analog Output
Figure 24. Pixel Output Timing using Two Analog Outputs
on page 20)
Figure
24). The
Multiplexing to One Analog Output
The pixel signal at the OUT1 output becomes valid after five
SYS_CLOCK cycles when the internal X_SYNC (equal to start
of PIXEL_VALID output) appears (see
PIXEL_VALID and EOL/EOF pulses can be delayed by the user
through the DELAY register.
T1: Row blanking time
T2: 5 SYS_CLOCK cycles.
IBIS4-6600 CYII4SM6600AB
Figure
Page 25 of 34
25). The
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