LTC4253AIGN#TR Linear Technology, LTC4253AIGN#TR Datasheet - Page 24

• Manufacturer Part Number: LTC4253AIGN#TR
• Description: MS-Hot Swap/High Voltage, Neg. 48V Hot Swap With 1% UV, Sequencer
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN#TR

• Family Name: LTC4253A
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
LTC4253/LTC4253A
V
checks for OV < V
0.8V, GATE < V
TIMER < V
starts and the TIMER capacitor is charged by a 5µA current
source pull-up. At time point 3, TIMER reaches the V
threshold and the initial timing cycle terminates. The TIMER
capacitor is quickly discharged. At time point 4, the V
threshold is reached and the conditions of GATE < V
SENSE < V
the GATE start-up cycle begins. SS ramps up as dictated
by R
amplifier until SS crosses 20 • V
50µA sources into the external MOSFET gate and compen-
sation network. When the GATE voltage reaches the
MOSFET’s threshold, current begins flowing into the load
capacitor at time point 5. At time point 6, load current
reaches SS control level and the analog current limit loop
activates. Between time points 6 and 8, the GATE voltage
is servoed and the SENSE voltage is regulated at V
and soft-start limits the slew rate of the load current. If the
SENSE voltage (V
at time point 7, the circuit breaker TIMER activates. The
TIMER capacitor, C
current pull-up. As the load capacitor nears full charge, load
current begins to decline. At point 8, the load current falls
and the SENSE voltage drops below V
current limit loop shuts off and the GATE pin ramps fur-
ther. At time point 9, the SENSE voltage drops below V
and the fault TIMER ends, followed by a 5µA discharge
current source (cool-off). When GATE ramps past V
threshold at time point A, PWRGD1 pulls low, starting off
the PWRGD sequence. PWRGD2 pulls low at time point C
when EN2 is high and PWRGD1 is low for more than one
t
is high and PWRGD2 is low for more than one t
point B, GATE reaches its maximum voltage as determined
by V
24
SQT
UVHI
. PWRGD3 pulls low at time point D when EN2 and EN3
SS
IN
(V
.
• C
UV
SS
for the LTC4253A). In addition, the internal logic
TMRL
CB
; GATE is held low by the analog current limit
and SS < 20 • V
. When all conditions are met, initial timing
GATEL
SENSE
OVHI
U
T
, SENSE < V
is charged by a (200µA + 8 • I
(V
– V
OV
U
EE
for the LTC4253A), RESET <
) reaches the V
OS
OS
must be satisfied before
. Upon releasing GATE,
CB
W
, SS < 20 • V
ACL
(t). The analog
CB
SQT
U
threshold
. At time
OS
GATEL
ACL
GATEH
TMRH
TMRL
DRN
and
(t)
CB
)
,
Undervoltage Timing
In Figure 10 when the UV pin drops below V
V
LTC4253A shut down with TIMER, SS and GATE pulled
low. If current has been flowing, the SENSE pin voltage
decreases to zero as GATE collapses. When UV recovers
and clears V
an initial time cycle begins followed by a start-up cycle.
V
V
timing behavior as the UV pin timing except it looks at V
< (V
undervoltage lockout condition, both UV and OV com-
parators are held off. When V
the UV and OV comparators are enabled.
Overvoltage Timing
During normal operation, if the OV pin exceeds V
for the LTC4253A) as shown at time point 1 of Figure 11,
the TIMER and PWRGD status are unaffected; SS and
GATE pull down; load disconnects. At time point 2, OV
recovers and drops below the V
LTC4253A) threshold; GATE start-up begins. If the over-
voltage glitch is long enough to deplete the load capacitor,
time points 4 through 7 may occur.
Circuit Breaker Timing
In Figure 12a, the TIMER capacitor charges at 200µA if the
SENSE pin exceeds V
SENSE pin returns below V
V
Figure 12b, when TIMER exceeds V
down immediately and the chip shuts down. In Figure 12c,
multiple momentary faults cause the TIMER capacitor to
integrate and reach V
and the chip shuts down. During chip shutdown, the
LTC4253/LTC4253A latch TIMER high with a 5µA pull-up
current source.
UVHST
IN
IN
TMRH
undervoltage lockout comparator, UVLO has a similar
Undervoltage Lockout Timing
LKO
for the LTC4253A) at time point 1, the LTC4253/
– V
threshold, TIMER is discharged by 5µA. In
LKH
UVHI
) to shut down and V
(V
UV
CB
TMRH
for the LTC4253A) at time point 2,
but V
CB
followed by GATE pull down
IN
exits undervoltage lockout,
DRN
before TIMER reaches the
OVLO
IN
is less than 5V. If the
(V
> V
TMRH
OV
LKO
– V
, GATE pulls
to start. In an
OVHST
UVLO
OVHI
(V
425353afc
for the
(V
UV
OV
IN
–