LTC4253AIGN#TR Linear Technology, LTC4253AIGN#TR Datasheet - Page 8

• Manufacturer Part Number: LTC4253AIGN#TR
• Description: MS-Hot Swap/High Voltage, Neg. 48V Hot Swap With 1% UV, Sequencer
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN#TR

• Family Name: LTC4253A
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

PI FU CTIO S
LTC4253/LTC4253A
EN2 (Pin 1): Power Good Status Output Two Enable. This
is a TTL compatible input that is used to control PWRGD2
and PWRGD3 outputs. When EN2 is driven low, both
PWRGD2 and PWRGD3 will go high. When EN2 is driven
high, PWRGD2 will go low provided PWRGD1 has been
active for more than one power good sequence delay
(t
to control the power good sequence. This pin is internally
pulled low by a 120µA current source.
PWRGD2 (Pin 2): Power Good Status Output Two. Power
good sequence starts with PWRGD1 latching active low.
PWRGD2 will latch active low after EN2 goes high and after
one power good sequence delay t
sequencing timer from the time PWRGD1 goes low,
whichever comes later. PWRGD2 is reset by PWRGD1
going high or EN2 going low. This pin is internally pulled
high by a 50µA current source.
PWRGD1 (Pin 3): Power Good Status Output One. At
start-up, PWRGD1 latches active low and starts the power
good sequence when the DRAIN pin is below 2.39V and
GATE is within 2.8V of V
V
time-out. This pin is internally pulled high by a 50µA
current source.
V
positive side of the supply through a dropping resistor. A
shunt regulator clamps V
undervoltage lockout (UVLO) circuit holds GATE low until
the V
UV is high, OV is low and V
starts an initial timing cycle before initiating GATE ramp
up. If V
LTC4253A), GATE pulls low immediately.
RESET (Pin 5): Circuit Breaker Reset Pin. This is an
asynchronous TTL compatible input. RESET going high
will pull GATE, SS, TIMER, SQTIMER low and the PWRGD
outputs high. The RESET pulse must be wide enough to
discharge any voltage on the TIMER pin below V
After the reset of a latched fault, the chip waits for the
interlock conditions before recovering as described in
Interlock Conditions in the Operation section.
8
IN
IN
SQT
U
(Pin 4): Positive Supply Input. Connect this pin to the
(UVLO), RESET going high or circuit breaker fault
) provided by the sequencing timer. EN2 can be used
IN
IN
pin is greater than V
drops below approximately 8.2V (8.5V for the
U
U
IN
IN
. PWRGD1 status is reset by UV,
IN
at 13V above V
LKO
comes out of UVLO, TIMER
, overriding UV and OV. If
SQT
provided by the
EE
. An internal
TMRL
.
SS (Pin 6): Soft-Start Pin. This pin is used to ramp inrush
current during start up, thereby effecting control over
di/dt. A 20X attenuated version of the SS pin voltage is
presented to the current limit amplifier. This attenuated
voltage limits the MOSFET’s drain current through the
sense resistor during the soft-start current limiting. At the
beginning of the start-up cycle, the SS capacitor (C
ramped by a 22µA (28µA for the LTC4253A) current
source. The GATE pin is held low until SS exceeds 20 • V
= 0.2V. SS is internally shunted by a 100k R
the SS pin voltage to 2.2V (50k resistor and 1.4V for the
LTC4253A). This corresponds to an analog current limit
SENSE voltage of 100mV (60mV for the LTC4253A). If the
SS capacitor is omitted, the SS pin ramps up in about
250µs (140µs for the LTC4253A). The SS pin is pulled low
under any of the following conditions: UVLO at V
OV, during the initial timing cycle, a circuit breaker fault
time-out or the RESET pin going high.
SENSE (Pin 7): Circuit Breaker/Current Limit Sense Pin.
Load current is monitored by a sense resistor R
nected between SENSE and V
steps. If SENSE exceeds V
comparator activates a (200µA + 8 • I
current. If SENSE exceeds V
amplifier pulls GATE down to regulate the MOSFET current
at V
SENSE may overshoot V
(200mV), the fast current-limit comparator pulls GATE
low with a strong pull-down. To disable the circuit breaker
and current limit functions, connect SENSE to V
V
pin to the negative side of the power supply.
GATE (Pin 9): N-channel MOSFET Gate Drive Output. This
pin is pulled high by a 50µA current source. GATE is pulled
low by invalid conditions at V
initial timing cycle, a circuit breaker fault time-out or the
RESET pin going high. GATE is actively servoed to control
the fault current as measured at SENSE. Compensation
capacitor, C
monitors GATE to ensure that it is low before allowing an
initial timing cycle, then the GATE ramps up after an
overvoltage event or restart after a current limit fault.
EE
(Pin 8): Negative Supply Voltage Input. Connect this
ACL
/R
S
. In the event of a catastrophic short-circuit,
C
, at GATE stabilizes this loop. A comparator
CB
ACL
IN
ACL
(50mV), the circuit breaker
EE
. If SENSE reaches V
(UVLO), UV, OV, during the
, the analog current-limit
, and controlled in three
DRN
) TIMER pull-up
SS
which limits
EE
IN
S
.
425353afc
SS
, UV,
con-
) is
FCL
OS