WM8973LGEFL/V Wolfson Microelectronics, WM8973LGEFL/V Datasheet - Page 41

• Manufacturer Part Number: WM8973LGEFL/V
• Description: Audio CODECs Stereo Codec with H/P Spkr
• Manufacturer: Wolfson Microelectronics

Specifications of WM8973LGEFL/V

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Advanced Information
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CLOCKING AND SAMPLE RATES
MASTER MODE ADCLRC AND DACLRC ENABLE
In Master mode, by default ADCLRC is disabled when the ADC is disabled and DACLRC is disabled
when the DAC is disabled. Register bit LRCM, register 24(18h) bit[2] changes the control so that the
ADCLRC and DACLRC are disabled only when ADC and DAC are disabled. This enables the user to
use e.g. ADCLRC for both ADC and DAC LRCLK and disable the ADC when DAC only operation is
required, (see Table 35).
Table 35 ADCLRC/DACLRC Enable
CLOCK OUTPUT
By default ADCLRC (pin 9) is the ADC word clock input/output. Under the control of ADCLRM[1:0],
register 27(1Bh) bits [8:7] the ADCLRC pin may be configured as a clock output. If ADCLRM is 01,
10 or 11 then ADCLRC pin is always an output even in slave mode or when TRI = ‘1’, (see Table 36).
Table 36 ADCLRC Clock Output
The WM8973L supports a wide range of master clock frequencies on the MCLK pin, and can
generate many commonly used audio sample rates directly from the master clock. The ADC and
DAC do not need to run at the same sample rate; several different combinations are possible.
There are two clocking modes:
Table 37 Clocking and Sample Rate Control
The clocking of the WM8973L is controlled using the CLKDIV2, USB, and SR control bits. Setting the
CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode.
Each value of SR[4:0] selects one combination of MCLK division ratios and hence one combination
of sample rates (see next page). Since all sample rates are generated by dividing MCLK, their
R24(18h)
Additional
Control (2)
R27(18h)
Additional
Control (3)
R8 (08h)
Clocking and
Sample Rate
Control
REGISTER
REGISTER
ADDRESS
ADDRESS
REGISTER
ADDRESS
‘Normal’ mode supports master clocks of 128f
(Note: f
USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in
systems with a USB interface, and eliminates the need for an external PLL to generate
another clock frequency for the audio CODEC.
s
refers to the ADC or DAC sample rate, whichever is faster)
[8:7] ADCLRM
BIT
BIT
2
6
5:1
0
LABEL
BIT
LABEL
LRCM
[1:0]
CLKDIV2
SR [4:0]
USB
DEFAULT
DEFAULT
LABEL
00
0
Selects disable mode for ADCLRC and
DACLRC
0 = ADCLRC disabled when ADC (Left and
1 = ADCLRC and DACLRC disabled only when
Configures ADCLRC pin
00 = ADCLRC is ADC word clock input (slave
mode) or ADCLRC output (master mode)
01 = ADCLRC pin is MCLK output
10 = ADCLRC pin is MCLK / 5.5 output
11 = ADCLRC pin is MCLK / 6 output
0
00000
0
s
DEFAULT
, 192f
Right) disabled, DACLRC disabled when
DAC (Left and Right) disabled.
ADC (Left and Right) and DAC (Left and
Right) are disabled.
s
, 256f
s
, 384f
DESCRIPTION
DESCRIPTION
Master Clock Divide by 2
1 = MCLK is divided by 2
0 = MCLK is not divided
Sample Rate Control
Clocking Mode Select
1 = USB Mode
0 = ‘Normal’ Mode
s
, and their multiples
DESCRIPTION
AI Rev 3.2 July 2004
WM8973L
41