WM8973LGEFL/V Wolfson Microelectronics, WM8973LGEFL/V Datasheet - Page 45

• Manufacturer Part Number: WM8973LGEFL/V
• Description: Audio CODECs Stereo Codec with H/P Spkr
• Manufacturer: Wolfson Microelectronics

Specifications of WM8973LGEFL/V

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Advanced Information
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POWER MANAGEMENT
The WM8973L has two control registers that allow users to select which functions are active. For
minimum power consumption, unused functions should be disabled. To avoid any pop or click noise,
it is important to enable or disable functions in the correct order (see Applications Information).
VMIDSEL is the enable for the Vmid reference, which defaults to disabled and can be enabled as a
50kOhm potential divider or, for low power maintenance of Vref when all other blocks are disabled,
as a 500kOhm potential divider.
Table 41 Power Management
STOPPING THE MASTER CLOCK
In order to minimise power consumed in the digital core of the WM8973L, the master clock should be
stopped in Standby and OFF modes. If this is cannot be done externally at the clock source, the
DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In
Standby mode with all supplies at 3.3V, setting DIGENB saves approximately 0.27mA on DCVDD
and 0.2mA on DBVDD. However, since setting DIGENB has no effect on the power consumption of
other system components external to the WM8973L, it is preferable to disable the master clock at its
source wherever possible.
Table 42 ADC and DAC Oversampling Rate Selection
NOTE: Before DIGENB can be set, the control bits ADCL, ADCR, DACL and DACR must be set
to zero and a waiting time of 1ms must be observed. Any failure to follow this procedure may
prevent DACs and ADCs from re-starting correctly.
R25 (19h)
Additional Control
(1)
R25 (19h)
Power
Management
(1)
R26 (1Ah)
Power
Management
(2)
Note: All control bits are 0=OFF, 1=ON
* The left mixer is enabled when LOUT1=1 or LOUT2=1. The right mixer is enabled when
ROUT1=1 or ROUT2=1.
REGISTER
ADDRESS
REGISTER
ADDRESS
8:7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
BIT
0
BIT
VMIDSEL
VREF
AINL
AINR
ADCL
ADCR
MICB
DACL
DACR
LOUT1
ROUT1
LOUT2
ROUT2
MONO
OUT3
LABEL
DIGENB
LABEL
DEFAULT
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DEFAULT
Vmid divider enable and select
00 – Vmid disabled (for OFF mode)
01 – 50kOhm divider enabled (for
10 – 500kOhm divider enabled (for low-
power
11 – 5kOhm divider enabled (for fast start-
up)
VREF (necessary for all other functions)
Analogue in PGA Left
Analogue in PGA Right
ADC Left
ADC Right
MICBIAS
DAC Left
DAC Right
LOUT1 Output Buffer*
ROUT1 Output Buffer*
LOUT2 Output Buffer*
ROUT2 Output Buffer*
MONOOUT Output Buffer and Mono Mixer
OUT3 Output Buffer
playback/record)
standby)
Master clock disable
0: master clock enabled
1: master clock disabled
DESCRIPTION
DESCRIPTION
AI Rev 3.2 July 2004
WM8973L
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