CS42418-CQZR Cirrus Logic Inc, CS42418-CQZR Datasheet - Page 38
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CS42418-CQZR
Manufacturer Part Number
CS42418-CQZR
Description
Audio CODECs IC 192kHz 110dB 6Ch Multi-Ch CODEC
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS42418-CQZ.pdf
(73 pages)
Specifications of CS42418-CQZR
Number Of Adc Inputs
2
Number Of Dac Outputs
8
Conversion Rate
192 KSPs
Interface Type
Serial (I2C, SPI)
Resolution
24 bit
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC, 8 DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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CS42418
4.9
Power Supply, Grounding, and PCB Layout
As with any high-resolution converter, the CS42418 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure
5
and
6
show the recommended power
arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be run from
the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this
case, no additional devices should be powered from VD.
For applications where the output of the PLL is required to be low jitter, use a separate, low-noise analog
+5 V supply for VA, decoupled to AGND. In addition, a separate region of analog ground plane around the
FILT+, VQ, LPFLT, REFGND, AGND, and VA pins is recommended.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42418 as pos-
sible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same
side of the board as the CS42418 to minimize inductance effects. All signals, especially clocks, should be
kept away from the FILT+, VQ and LPFLT pins in order to avoid unwanted coupling into the modulators and
PLL. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the
electrical path from FILT+ and REFGND. The CDB42428 evaluation board demonstrates the optimum lay-
out and power supply arrangements.
38
DS603F1