CS4220-KSZR Cirrus Logic Inc, CS4220-KSZR Datasheet - Page 20

• Manufacturer Part Number: CS4220-KSZR
• Description: Audio CODECs IC 24Bit Str Audio CODEC 3V Intrfc
• Manufacturer: Cirrus Logic Inc

Specifications of CS4220-KSZR

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-28
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC, 2 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7. PIN DESCRIPTIONS — CS4221
20
NC
XTI, XTO
LRCK
SCLK
VD
DGND
SDOUT
1,14,15, 28 No Connect - These pins are not connected internally and should be tied to DGND to mini-
2,3
4
5
6
7
8
mize noise coupling.
Crystal Connections ( Input/Output ) - Input and output connections for the crystal used to
clock the CS4221. Alternatively a clock may be input into XTI. This is the clock source for the
delta-sigma modulator and digital filters. The frequency of this clock must be either 256x, 384x,
or 512x Fs. The default XTI setting in Master Mode is 256x, but this may be changed to 384x
or 512x through the Control Port.
Left/Right Clock ( Input ) - Determines which channel is currently being input/output of the
serial audio data pins SDIN/SDOUT. The frequency of the Left/Right clock must be equal to the
input sample rate. Although the outputs for each ADC channel are transmitted at different
times, Left/Right pairs represent simultaneously sampled analog inputs. The required relation-
ship between the left/right clock, serial clock and serial data is defined by the DSP Port Mode
(05h) register. The options are detailed in Figures 8 - 11.
Serial Data Clock ( Input ) - Clocks the individual bits of the serial data into the SDIN pin and
out of the SDOUT pin. The required relationship between the left/right clock, serial clock and
serial data is defined by the DSP Port Mode (05h) register. The options are detailed in Figures
8 - 11.
Digital Power ( Input ) - Positive power supply for the digital section. Typically 5.0 VDC.
Digital Ground ( Input ) - Digital ground for the digital section.
Serial Data Output ( Output ) - Two’s complement MSB-first serial data is output on this pin.
The required relationship between the left/right clock, serial clock and serial data is defined by
the DSP Port Mode (05h) register. The options are detailed in Figures 8 - 11.
Fs (kHz)
44.1
32
48
SCL/CCLK
SDA/CDIN
AD0/CS
SDOUT
DGND
LRCK
SCLK
SDIN
XTO
Table 5. Common Clock Frequencies
XTI
NC
NC
VD
VL
11.2896
12.2880
1
2
3
4
5
6
7
8
9
10
11
12
13
14
8.1920
256x
CS4221
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
RST
AOUTL-
AOUTL+
AOUTR+
AOUTR-
AGND
VA
AINL+
AINL-
I2C/SPI
AINR+
AINR-
NC
XTI (MHz)
12.2880
16.9344
18.4320
384x
16.3840
22.5792
24.5760
512x
CS4220 CS4221
DS284PP3