DS26502LN Maxim Integrated Products, DS26502LN Datasheet - Page 104

• Manufacturer Part Number: DS26502LN
• Description: Timers & Support Products E1-T1-J1-64KCC BITS Element 64kHz - G.70
• Manufacturer: Maxim Integrated Products
• Type: Clock Recoveryr

Specifications of DS26502LN

• Supply Voltage (max): 3.46 V
• Supply Voltage (min): 3.13 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 85 mA
• Package / Case: LQFP-64

IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test
register is selected. The device identification code will be loaded into the identification register on the
rising edge of JTCLK following entry into the capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During test-logic-reset, the identification code is forced into the
instruction register’s parallel output. The ID code will always have a 1 in the LSB position. The next 11
bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for
the device and 4 bits for the version
Table 17-2. ID Code Structure
MSB
Table 17-3. Device ID Codes
DS26502
17.2 Test Registers
IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register.
An optional test register has been included with the DS26502 design. This test register is the
identification register and is used with the IDCODE instruction and the test-logic-reset state of the TAP
controller.
17.2.1 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is n bits in length. See for all the cell bit locations and definitions.
17.2.2 Bypass Register
This is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that
provides a short path between JTDI and JTDO.
17.2.3 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the test-logic-reset state.
Contact Factory
Version
4 bits
DEVICE
Device ID
16 bits
16-BIT ID
Table
0035h
17-2.
104 of 125
Table 17-3
00010100001
JEDEC
lists the device ID codes.
LSB
1
1