DS26502LN Maxim Integrated Products, DS26502LN Datasheet - Page 84

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DS26502LN

Manufacturer Part Number
DS26502LN
Description
Timers & Support Products E1-T1-J1-64KCC BITS Element 64kHz - G.70
Manufacturer
Maxim Integrated Products
Type
Clock Recoveryr
Datasheet

Specifications of DS26502LN

Supply Voltage (max)
3.46 V
Supply Voltage (min)
3.13 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Current
85 mA
Package / Case
LQFP-64

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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bit 0: Custom Line Driver Select (CLDS). Setting this bit to a one will redefine the operation of the transmit line driver.
When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1.7 = 0, then the device will generate a square wave at the TTIP and
TRING outputs instead of a normal waveform. When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1.7 ≠ 0, then the device
will force TTIP and TRING outputs to become open-drain drivers instead of their normal push-pull operation. This bit should
be set to zero for normal operation of the device. Note: This bit should be set = 0 in 64KCC and 6312kHz transmit modes.
Bit 1: Short Circuit Limit Disable (in E1 mode) (SCLD). Controls the 50mA (rms) current limiter. Note: Not applicable in
6312kHz mode.
Bit 2: Receive Composite Clock Filter Enable (RCCFE). (64KCC mode only) Setting this bit will enable the PLL filter on
the received 64kHz composite clock. Note: the 8kHz and 400Hz output are not filtered.
Bit 3: Jitter Attenuator Clock Select 0 (JACKS0). This bit, along with JACKS1 (LIC2.7), MPS0 (LIC4.6), and MPS1
(LIC4.7), controls the source for JA CLOCK from the MCLK pin. Note: This bit must be configured even if the jitter
attenuator is disabled. The clock and data recovery engine also uses the JA CLOCK. Setting this bit enables the 2.048MHz to
1.544MHz conversion PLL for T1 applications. See the table in the LIC4 register description for more details on setting up the
JA CLOCK source.
Bit 4: Transmit Alarm Indication Signal (TAIS)
Bit 5: Insert BPV (IBPV). A zero-to-one transition on this bit will cause a single BPV to be inserted into the transmit data
stream. Once this bit has been toggled from a zero to a one, the device waits for the next occurrence of three consecutive ones
to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted. Note: This function not
supported in 64KCC and 6312kHz modes.
Bit 6: Line Interface Reset (LIRST). Setting this bit from a zero to a one will initiate an internal reset that resets the clock
recovery state machine and recenters the jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and
set again for a subsequent reset.
Bit 7: Jitter Attenuator Clock Select 1 (JACKS1). This bit, along with JACKS0 (LIC2.3), MPS0 (LIC4.6), and MPS1
(LIC4.7), controls the source for JA CLOCK from the MCLK pin. Note: This bit must be configured even if the jitter
attenuator is disabled. The clock and data recovery engine also uses the JA CLOCK. Setting this bit enables the 12.8MHz to
2.048MHz conversion PLL. See the table in the LIC4 register description for more details on setting up the JA CLOCK source.
0 = enable 50mA current limiter
1 = disable 50mA current limiter
0 = Receive Composite Clock Filter Disabled
1 = Receive Composite Clock Filter Enabled
0 = 2.048MHz to 1.544MHz PLL bypassed
1 = 2.048MHz to 1.544MHz PLL enabled
0 = transmit an unframed all-ones code
1 = transmit data normally
0 = 12.8MHz to 2.048MHz PLL bypassed
1 = 12.8MHz to 2.048MHz PLL enabled
JACKS1
7
0
0
LIRST
LIC2
Line Interface Control 2
31h
6
0
0
IBPV
5
0
0
PIN 10
TAIS
TAIS
4
0
84 of 125
JACKS0
JACKS
PIN 46
3
0
RCCFE
2
0
0
SCLD
1
0
0
CLDS
0
0
0

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