CY28442ZXC-2 Silicon Laboratories Inc, CY28442ZXC-2 Datasheet - Page 6

• Manufacturer Part Number: CY28442ZXC-2
• Description: Clock Generators & Support Products Calistoga
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28442ZXC-2

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 21, 2006
Byte 3: Control Register 3
Byte 4: Control Register 4
Byte 5: Control Register 5
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
@Pup
@Pup
@Pup
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
SRC[T/C][7:1]
96_100_SSC
RESERVED
RESERVED
DOT96T/C
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
CPU[T/C]2
CPU[T/C]1
SRC[T/C]
Name
PCIF1
PCIF0
Name
SRC7
SRC6
SRC5
SRC4
SRC3
SRC2
SRC1
Name
CPU[T/C]2 Stop Drive Mode
CPU[T/C]1 Stop Drive Mode
CPU[T/C]0 Stop Drive Mode
CPU[T/C]2 PWRDWN Drive Mode
CPU[T/C]1 PWRDWN Drive Mode
Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED
96_100_SSC Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
RESERVED
Allow control of PCIF1 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP#
asserted
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
0 = Driven when PD asserted,1 = Tri-state when PD asserted
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Description
Description
Description
CY28442-2
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