LX64EV-5FN100I Lattice, LX64EV-5FN100I Datasheet - Page 35

• Manufacturer Part Number: LX64EV-5FN100I
• Description: Analog & Digital Crosspoint ICs E-Series, 64 I/O Switch Matrix, 3.3V, 5ns, IND, Pb-Free
• Manufacturer: Lattice

Specifications of LX64EV-5FN100I

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 64 x 64
• Package / Case: FPBGA-100
• Data Rate: 11 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Sample External Timing Calculations
The following equations illustrate the task of determining the timing through the ispGDX2 family. These are only a
sample of equations to calculate the timing through the ispGDX2.
Figure 18 shows the specific delay paths and the Internal Timing Parameters table provides the parameter values.
Note that the internal timing parameters are given for reference only and are not tested. The external timing param-
eters are tested and guaranteed for every device.
Data from global select pin to output pin:
t
Global clock to output:
t
Input register or latch set-up time before global clock:
t
Input register or latch hold time after global clock:
t
Data from product term select to output pin:
t
Product term clock to output:
t
Input register or latch set-up time before product term clock:
t
Input register or latch hold time after product term clock:
t
Global OE input to output enable/disable:
t
External reset pin to output delay:
t
PD_SEL
CO
IPS
IPH
PD_PTSEL
CO_PT
IPS_PT
IPH_PT
GOE/DIS
OPRSTO
= t
= t
= (t
CLK_IN
IN
= t
= t
CLK_IN
= (t
= t
= t
= t
+ t
IN
IN
= t
SEL_IN
IN
GOE_IN
SR_IN
IPS
+ t
+ t
IN
+ t
+ t
+ t
IPBYPASS
IPSi_PT
- (t
+ t
IPBYPASS
GCLK
GCLK
+ t
+ t
CLK
IPBYPASS
+ t
OPASROi
MUXSEL
OEBYPASS
+ t
) + t
+ t
- (t
OPCOi
+ t
GCLK
IN
+ t
IPHi
ROUTEGRP
+ t
+ t
ROUTEGRP
+ t
+ t
)
- t
ROUTEGRP
IPBYPASS
+ t
OPBYPASS
BUF
+ t
IN
BUF
EN
+ t
+ t
+ t
PTCLK
+ t
+ t
PTCLK
ROUTEGRP
PTSEL
BUF
+ t
) + t
OPCOi
+ t
IPHi
MUXSEL
+ t
- t
PTCLK
+ t
32
IN
BUF
+ t
)
OPBYPASS
+ t
BUF
ispGDX2 Family Data Sheet