LX256EV-5FN484I Lattice, LX256EV-5FN484I Datasheet - Page 38

• Manufacturer Part Number: LX256EV-5FN484I
• Description: Analog & Digital Crosspoint ICs E-Series, 256 I/O Switch Matrix, 3.3V, 5ns, IND, Pb-Free
• Manufacturer: Lattice

Specifications of LX256EV-5FN484I

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 256 x 256
• Package / Case: FPBGA-484
• Data Rate: 38 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters
Lattice Semiconductor
t
t
t
t
t
1. Internal parameters are not tested and are for reference only. Refer to the timing model in this data sheet for details.
2. t
OELSi
OELSi_PT
OESi
OESi_PT
OESRPWi
Parameter
given in the sysCLOCK PLL Timing section) in either direction in steps of size t
PLL_DELAY
is the unit of increment by which the clock signal can be incremented. The PLL can adjust the clock signal by up to t
Latch Setup Time (Global Gate)
Latch Setup Time (Product Term Gate)
Register Setup Time (Global Clock)
Register Setup Time (Product Term Clock)
Asynchronous Set/Reset Pulse Width
Description
Over Recommended Operating Conditions
35
Min.
1.40
1.00
1.00
1.00
—
-3
Max.
2.50
—
—
—
—
PLL_DELAY.
Min.
1.40
1.00
1.00
1.00
—
-32
Max.
2.50
—
—
—
—
ispGDX2 Family Data Sheet
Min.
1.40
1.00
1.40
1.00
—
-35
Max.
2.50
—
—
—
—
1
(Continued)
Min.
2.33
1.67
2.33
1.67
—
-5
Max.
4.17
—
—
—
—
RANGE
Timing v.2.2
Units
(as
ns
ns
ns
ns
ns