LX256V-5FN484C Lattice, LX256V-5FN484C Datasheet - Page 30

• Manufacturer Part Number: LX256V-5FN484C
• Description: Analog & Digital Crosspoint ICs 256 I/O Switch Matrix, 3.3V, SERDES, 5ns, Pb-Free
• Manufacturer: Lattice

Specifications of LX256V-5FN484C

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 256 x 256
• Package / Case: FPBGA-484
• Data Rate: 38 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispGDX2V/B/C, ispGDX2EV/EB/EC External Switching Characteristics
Output Paths
t
t
t
t
t
t
t
t
Input Paths
t
t
t
t
t
t
t
Output Enable Paths
t
t
t
t
t
t
t
t
Clock and Reset Paths
t
t
t
f
f
No PLL)
Parameter
PD
PD_SEL
CO
OPS
OPH
OPCES
OPCEH
OPRSTO
IPS
IPSZ
IPH
IPHZ
IPCES
IPCEH
IPRSTO
OECO
OES
OEH
OECES
OECEH
GOE/DIS
TOE/DIS
EN/DIS
RW
CW
GW
MAX
MAX
(Ext)
(Tog,
Data From Input Pin to Output Pin
Data From Global Select Pin to Output Pin
Global Clock to Output
Set-up Time Before Global Clock
Hold Time After Global Clock
PT Clock Enable Setup Time Before
Global Clock
PT Clock Enable Hold Time After
Global Clock
External Reset Pin to Output Delay
Set-up Time Before Global Clock
Set-up Time Before Global Clock
(Zero Hold Time)
Hold Time After Global Clock
Hold Time After Global Clock
(Zero Hold Time)
PT Clock Enable Setup Time Before
Global Clock
PT Clock Enable Hold Time After Global
Clock
External Reset Pin to Output Delay
Global Clock to Output Enabled Pin
Output Enable Register Set-up Time
Before Global Clock
Hold Time After Global Clock
PT Clock Enable Setup Time Before
Global Clock
PT Clock Enable Hold Time After Global
Clock
Global OE Input to Output Enable/Disable
Test OE Input to Output Enable/Disable
Input to Output Enable/Disable
Width of Reset Pulse
Clock Width
Clock Width
Clock Frequency with External
Feedback 1/(t
Clock Frequency Maximum Toggle
(No PLL)
OPS
Description
+ t
CO
)
Over Recommended Operating Conditions
Min.
2.0
0.0
3.0
0.0
0.5
2.0
1.0
0.0
3.1
0.0
1.6
0.0
3.5
0.0
2.5
1.3
1.5
—
—
—
—
—
—
—
—
—
—
—
27
-3
Max.
204
360
3.0
2.8
2.9
5.3
5.6
4.2
3.5
5.2
5.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
2.0
0.0
3.0
0.0
0.5
2.0
1.0
0.0
3.1
0.0
1.6
0.0
3.5
0.0
2.5
1.5
1.6
—
—
—
—
—
—
—
—
—
—
—
-32
Max.
196
330
3.2
3.0
3.1
6.0
6.5
4.5
3.8
5.5
5.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ispGDX2 Family Data Sheet
Min.
2.0
0.0
4.1
0.0
0.5
2.0
1.0
0.0
3.1
0.0
2.0
0.0
4.1
0.0
2.5
1.6
1.6
—
—
—
—
—
—
—
—
—
—
—
-35
Max.
192
300
3.2
6.0
7.5
5.5
6.2
3.5
3.3
4.5
6.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
3.0
0.0
6.9
0.0
0.9
3.0
1.7
0.0
5.1
0.0
3.4
0.0
6.9
0.0
4.1
2.7
2.7
—
—
—
—
—
—
—
—
—
—
—
-5
Max.
10.0
12.5
10.3
10.3
119
180
5.0
4.7
5.4
9.1
7.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns